[v3,00/20] coresight: Add support for CPU-wide trace scenarios

Message

Mathieu Poirier April 4, 2019, 3:35 a.m. UTC

This is the third revision of a patchset that adds support for CPU-wide
trace scenarios and as such, it is now possible to issue the following
commands:

        # perf record -e cs_etm/@20070000.etr/ -C 2,3 $COMMAND
        # perf record -e cs_etm/@20070000.etr/ -a $COMMAND

The solution is designed to work for both 1:1 and N:1 source/sink
topologies, though the former hasn't been tested for lack of access to HW.

Most of the changes revolve around allowing more than one event to use
a sink when operated from perf.  More specifically the first event to
use a sink switches it on while the last one is tasked to aggregate traces
and switching off the device.

This is the kernel part of the solution, with the user space portion to be
released in a later set.  All patches (user and kernel) have been rebased
on v5.1-rc3 and are hosted here[1].  Everything has been tested on Juno, the
410c dragonboard, and hikey620 platforms.

Regards,
Mathieu

[1]. https://git.linaro.org/people/mathieu.poirier/coresight.git (5.1-rc3-cpu-wide-v3) 

== Changes for v3 ==
* Added review-by tags (some were dropped due to patch refactoring).
* Split IDR and reference counting patches.
* Moved IDR to struct tmc_drvdata to support 1:1 source/sink topologies.
* Enhanced code comments related to design choices.
* Renamed ETR buffer allocation functions to have a stronger perf semantic.
* Rebased to v5.1-rc3.

== Changes for V2 ==
* Using define ETM4_CFG_BIT_CTXTID rather than hard coded value (Suzuki).
* Moved pid out of struct etr_buf and into struct etr_perf_buffer (Suzuki).
* Removed code related to forcing double buffering (Suzuki).
* Fixed function reallocarray() for older distributions (Mike).
* Fixed counter configuration when dealing with errors(Leo).
* Automatically selecting PID_IN_CONTEXTIDR with ETMv4 driver.
* Rebased to v5.1-rc2.

Mathieu Poirier (20):
  coresight: pmu: Adding ITRACE property to cs_etm PMU
  coresight: etm4x: Add kernel configuration for CONTEXTID
  coresight: etm4x: Skip selector pair 0
  coresight: etm4x: Configure tracers to emit timestamps
  coresight: Adding return code to sink::disable() operation
  coresight: Move reference counting inside sink drivers
  coresight: Properly address errors in sink::disable() functions
  coresight: Properly address concurrency in sink::update() functions
  coresight: perf: Clean up function etm_setup_aux()
  coresight: perf: Refactor function free_event_data()
  coresight: Communicate perf event to sink buffer allocation functions
  coresight: tmc-etr: Refactor function tmc_etr_setup_perf_buf()
  coresight: tmc-etr: Create per-thread buffer allocation function
  coresight: tmc-etr: Introduce the notion of process ID to ETR devices
  coresight: tmc-etr: Introduce the notion of reference counting to ETR
    devices
  coresight: tmc-etr: Introduce the notion of IDR to ETR devices
  coresight: tmc-etr: Allocate and free ETR memory buffers for CPU-wide
    scenarios
  coresight: tmc-etr: Add support for CPU-wide trace scenarios
  coresight: tmc-etf: Add support for CPU-wide trace scenarios
  coresight: etb10: Add support for CPU-wide trace scenarios

 drivers/hwtracing/coresight/Kconfig           |   1 +
 drivers/hwtracing/coresight/coresight-etb10.c |  83 ++++--
 .../hwtracing/coresight/coresight-etm-perf.c  |  37 ++-
 drivers/hwtracing/coresight/coresight-etm4x.c | 113 +++++++-
 .../hwtracing/coresight/coresight-tmc-etf.c   |  82 ++++--
 .../hwtracing/coresight/coresight-tmc-etr.c   | 261 ++++++++++++++++--
 drivers/hwtracing/coresight/coresight-tmc.c   |   6 +
 drivers/hwtracing/coresight/coresight-tmc.h   |  12 +
 drivers/hwtracing/coresight/coresight-tpiu.c  |   9 +-
 drivers/hwtracing/coresight/coresight.c       |  28 +-
 include/linux/coresight-pmu.h                 |   2 +
 include/linux/coresight.h                     |   7 +-
 tools/include/linux/coresight-pmu.h           |   2 +
 13 files changed, 546 insertions(+), 97 deletions(-)