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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id z14sm1510110wro.81.2019.04.18.05.27.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Apr 2019 05:27:23 -0700 (PDT) From: Jerome Brunet To: Kevin Hilman Subject: [PATCH 0/6] arm64: dts: meson: mmc clean-up Date: Thu, 18 Apr 2019 14:27:08 +0200 Message-Id: <20190418122714.30805-1-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190418_052726_106487_7779CF59 X-CRM114-Status: UNSURE ( 8.88 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, patchwork-bot+notify@kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Jerome Brunet Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The patchset is bunch of clean-up found while debugging meson mmc. * The first 2 patches address the libretech-cc which actually uses 1.8v eMMC modules. * Patch 3 is a pin bias fixup depending on mmc pins. * Patch 4 lower the mmc max frequencies on gx chips. It was not easy to spot but, according to the datasheet, the maximum UHS rate supported by these chips is 100MHz (SDR50). This explains why we never really managed to get a stable SDR104. SDIO is limited to HS. * Patch 5 adds missing pinctrl definition on the vim2 * Patch 6 remove hs400 from the supported modes of the vim2. This mode is mode reliable enough with HW/SW ATM. When/If the series on the mmc drivers goes through, I'll send the following updates: * Push odroid-c2 eMMC max rate from 100Mhz to 200Mhz. With the new tuning method, this mode is finally stable on the OC2 (so far...) * Enable SD UHS modes on the odroid-c2 * Enable SD UHS DDR50 on the nanopi k2 Jerome Brunet (6): arm64: dts: meson: libretech-cc: set eMMC as removable arm64: dts: meson: libretech-cc: switch eMMC to 1.8v arm64: dts: meson: fix mmc pin bias arm64: dts: meson: fix mmc v2 chips max frequencies arm64: dts: meson: vim2: add missing clk-gate pinctrl arm64: dts: meson: vim2: remove sd hs and hs400 modes from emmc .../arm64/boot/dts/amlogic/meson-axg-s400.dts | 4 +-- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 31 ++++++++++++---- .../boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 4 +-- .../boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 5 ++- .../dts/amlogic/meson-gxbb-nexbox-a95x.dts | 2 +- .../boot/dts/amlogic/meson-gxbb-p20x.dtsi | 2 +- .../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 4 +-- .../boot/dts/amlogic/meson-gxbb-wetek.dtsi | 4 +-- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 35 +++++++++++++------ .../boot/dts/amlogic/meson-gxl-s805x-p241.dts | 2 +- .../amlogic/meson-gxl-s905x-libretech-cc.dts | 14 ++++---- .../amlogic/meson-gxl-s905x-nexbox-a95x.dts | 2 +- .../dts/amlogic/meson-gxl-s905x-p212.dtsi | 4 +-- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 35 +++++++++++++------ .../dts/amlogic/meson-gxm-khadas-vim2.dts | 15 ++++---- .../boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 +- .../boot/dts/amlogic/meson-gxm-rbox-pro.dts | 4 +-- 17 files changed, 109 insertions(+), 60 deletions(-)