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Tue, 23 Apr 2019 22:20:11 -0700 From: Vidya Sagar To: , , , , , , , , , , Subject: [PATCH V5 00/16] Add Tegra194 PCIe support Date: Wed, 24 Apr 2019 10:49:48 +0530 Message-ID: <20190424052004.6270-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1556083210; bh=5gL56myZIf2UEG6Zqt1sc7+3e10peXUUHrOtE7cUP9k=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=DE8bCP0W+2plMWJbzYX3LW4Tm43bNAnEQ3LlKlfSCm1PLhc170sn/YBMUX2POU97N 4ZSpdKn4ge9tniZotzOmZgDrcUspf0+iDhjHpmaUK3zy/WDQtCeULw2WgeZdTZnMc1 jkItbjDmF6agAtyLKQRUhi4dX8tnmvw3KwTx4P8L2//afNXACN7UpO0l0UpuwlpYto 4XeBoGfWC9z/ckr96KL4yaZ5EWkHeS9KD8w6ZsbAA8SeSx8Hv6J+hbYaTU+miyvCSu y9E2zLeqppTaI1QDC9gJrm9vtv7u6Ek0Wr4asJMR01EukyXP94tz0BqAKg02DFW8in 11jv5naFN2PiQ== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190423_222014_300092_21B46B0B X-CRM114-Status: GOOD ( 12.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, mmaddireddy@nvidia.com, kthota@nvidia.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mperttunen@nvidia.com, linux-tegra@vger.kernel.org, vidyas@nvidia.com, linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra194 has six PCIe controllers based on Synopsys DesignWare core. There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO: Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively. Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses UPHY lanes from NVHS brick. Lane mapping in HSIO UPHY brick to each PCIe controller (0~4) is controlled in XBAR module by BPMP-FW. Since PCIe core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is used to connect each UPHY lane (applicable to both HSIO and NVHS UPHY bricks) to PCIe controller This patch series - Adds support for P2U PHY driver - Adds support for PCIe host controller - Adds device tree nodes each PCIe controllers - Enables nodes applicable to p2972-0000 platform - Adds helper APIs in Designware core driver to get capability regs offset - Adds defines for new feature registers of PCIe spec revision 4 - Makes changes in DesignWare core driver to get Tegra194 PCIe working Testing done on P2972-0000 platform - Able to get PCIe link up with on-board Marvel eSATA controller - Able to get PCIe link up with NVMe cards connected to M.2 Key-M slot - Able to do data transfers with both SATA drives and NVMe cards Note - Enabling x8 slot on P2972-0000 platform requires pinmux driver for Tegra194. It is being worked on currently and hence Controller:5 (i.e. x8 slot) is disabled in this patch series. A future patch series would enable this. - This series is based on top of the following series Jisheng's patches to add support to .remove() in Designware sub-system https://patchwork.kernel.org/project/linux-pci/list/?series=98559 (Jisheng's patches are now accepted and applied for v5.2) My patches made on top of Jisheng's patches to export various symbols https://patchwork.kernel.org/project/linux-pci/list/?series=101259 Changes since [v4]: * Removed redundant APIs in pcie-designware-ep.c file after moving them to pcie-designware.c file based on Bjorn's review comments Changes since [v3]: * Rebased on top of linux-next top of the tree * Addressed Gustavo's comments and added his Ack for some of the changes. Changes since [v2]: * Addressed review comments from Thierry Changes since [v1]: * Addressed review comments from Bjorn, Thierry, Jonathan, Rob & Kishon * Added more patches in v2 series Vidya Sagar (16): PCI: Add #defines for some of PCIe spec r4.0 features PCI/PME: Export pcie_pme_disable_msi() & pcie_pme_no_msi() APIs PCI: Export pcie_bus_config symbol PCI: dwc: Perform dbi regs write lock towards the end PCI: dwc: Move config space capability search API PCI: dwc: Add ext config space capability search API dt-bindings: PCI: designware: Add binding for CDM register check PCI: dwc: Add support to enable CDM register check Documentation/devicetree: Add PCIe supports-clkreq property dt-bindings: PCI: tegra: Add device tree support for T194 dt-bindings: PHY: P2U: Add Tegra 194 P2U block arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT arm64: tegra: Enable PCIe slots in P2972-0000 board phy: tegra: Add PCIe PIPE2UPHY support PCI: tegra: Add Tegra194 PCIe support arm64: Add Tegra194 PCIe driver to defconfig .../bindings/pci/designware-pcie.txt | 5 + .../bindings/pci/nvidia,tegra194-pcie.txt | 187 ++ Documentation/devicetree/bindings/pci/pci.txt | 5 + .../bindings/phy/phy-tegra194-p2u.txt | 28 + .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 41 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 449 +++++ arch/arm64/configs/defconfig | 1 + drivers/pci/controller/dwc/Kconfig | 11 + drivers/pci/controller/dwc/Makefile | 1 + .../pci/controller/dwc/pcie-designware-ep.c | 37 +- .../pci/controller/dwc/pcie-designware-host.c | 3 - drivers/pci/controller/dwc/pcie-designware.c | 87 + drivers/pci/controller/dwc/pcie-designware.h | 12 + drivers/pci/controller/dwc/pcie-tegra194.c | 1760 +++++++++++++++++ drivers/pci/pci.c | 1 + drivers/pci/pcie/pme.c | 14 +- drivers/pci/pcie/portdrv.h | 16 +- drivers/phy/tegra/Kconfig | 7 + drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/pcie-p2u-tegra194.c | 120 ++ include/uapi/linux/pci_regs.h | 22 +- 22 files changed, 2756 insertions(+), 54 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c create mode 100644 drivers/phy/tegra/pcie-p2u-tegra194.c