From patchwork Tue May 21 14:30:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 10953923 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3DF30112C for ; Tue, 21 May 2019 14:31:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2D394288C7 for ; Tue, 21 May 2019 14:31:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 20EF2286BF; Tue, 21 May 2019 14:31:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 94CEB287C2 for ; Tue, 21 May 2019 14:31:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=KwqAtOWvJC8dWQXAJnI4kbNWjWGrdi6XH1y/KxYKCsk=; b=MBj6w/up6cE0o+ BR0bC4rc7s10g6LDpcKTPsZPyU0fS6dVejIRa1PyPBF8GocvxFO4jF5TrU/XsCBq+rkvHLmNaqACU 27TdSWCqc+MfFJKok0Ei7pOmH9KOok61lZ3tN2vvuT11HYzMqUsouZC3OZPEjlLjWD0u6lufrdEXl vTdjhfDg/SuqWdScS9TXJRJZshPqpoMf7N2GyuTs5U3ba/55VUWp5RO+k4DaMaxJiWpLeNZQ9B5+w 5ST++61sBrI+hveGpNp/O7RR61JrARMIuKQuzQ7DQIn/18GanZ20tOCkkPM6J1j/BRH+EtauVyhLj GVPYdGgDeojCTHrgnfGQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hT5n6-0000eh-MD; Tue, 21 May 2019 14:30:56 +0000 Received: from relay1-d.mail.gandi.net ([217.70.183.193]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hT5n1-0000du-QC for linux-arm-kernel@lists.infradead.org; Tue, 21 May 2019 14:30:53 +0000 X-Originating-IP: 90.88.22.185 Received: from localhost.localdomain (aaubervilliers-681-1-80-185.w90-88.abo.wanadoo.fr [90.88.22.185]) (Authenticated sender: miquel.raynal@bootlin.com) by relay1-d.mail.gandi.net (Postfix) with ESMTPSA id 3FF9C240006; Tue, 21 May 2019 14:30:26 +0000 (UTC) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Rob Herring , Mark Rutland , Jens Axboe , Hans de Goede , Thomas Gleixner , Marc Zyngier Subject: [PATCH v4 00/10] Enable per-port SATA interrupts and drop a hack in the IRQ subsystem Date: Tue, 21 May 2019 16:30:13 +0200 Message-Id: <20190521143023.31810-1-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190521_073052_155714_89AC2484 X-CRM114-Status: GOOD ( 18.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Baruch Siach , Antoine Tenart , Maxime Chevallier , Nadav Haklai , linux-ide@vger.kernel.org, Thomas Petazzoni , Miquel Raynal , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Hello, Some time ago, when the initial support for Armada CP110 was contributed, the SATA core was not able to handle per-port interrupts. Despite the hardware reality, the device tree only represents one main interrupt for the two ports. Having both SATA ports enabled at the same time has been achieved by a hack in the ICU driver(1) that faked the use of the two interrupts, no matter which SATA port was in use. Now that the SATA core is ready to handle more than one interrupt, this series adds support for it in the libahci_platform code. The CP110 device tree must be updated to reflect the two SATA ports available and their respective interrupts. To do not break DT backward compatibility, the ahci_platform driver now embeds a special quirk which checks if the DT is valid (only for A8k compatible) and, if needed, creates the two missing sub-nodes, and assign them the relevant "reg" and "interrupts" properties, before removing the main SATA node "interrupts" one. Thanks, Miquèl (1) The ICU is an irqchip aggregating the CP110 (south-bridge) interrupts into MSIs for the AP806 (north-bridge). Changes in v4 ============= * Rebase on top of v5.2-rc1 * s/ARM64/arm64/ in the DT change commit title. Changes in v3 ============= * Removed useless locking when acking the SATA host IRQ_STAT bit. * As spotted by Hans, do not enable the AHCI_HFLAG_MULTI_MSI flag only if more than one port is enabled, DTs might declare only one interrupt and have multiple ports. Added Hans' Reviewed-by tag. * Added Rob's Reviewed-by tags. * Added explicit references to the 'Device Tree' being the culprit for the hacks which are being treated in patch "ata: ahci: mvebu: Add support for A8k legacy bindings" as suggested by Marc. * Modified all DTs to avoid enabling/disabling the SATA ports independently, which does not work. Either both ports are enabled, or none. Tested on MacchiatoBin that all three availabe ports on the board are functional. Changes in v2 ============= * In the AHCI world, the 'irq' is now an '*irqs' array, I ensured it is allocated even when not using *_platform drivers. * Moved the whole logic from the generic ahci_platform.c driver to the Marvell's ahci_mvebu.c driver. * Dropped the whole DT manipulation quirk. * Instead used a hack to configure both interrupts when using the deprecated bindings, this hack is a8k specific but there is a flag that is passed to the core during the ahci_platform_get_resources() to indicate that the number of ports must be forced to 2 no matter the number of child nodes. * The A8k based Clearfog-GT actually uses the SATA IP (Baruch's info) so do not remove the SATA node from the DT. Instead, change the DTS to fit the new bindings (the board only uses the second port at offset 1). * Added bindings documentation about the A8k AHCI compatible (existing in DTs, missing in the doc). * SATA Sub-nodes representing ports already are documented, I just added a mention that they can also have an interrupts property which is mutually exclusive with the root SATA node. Miquel Raynal (9): ata: libahci: Ensure the host interrupt status bits are cleared ata: ahci: Support per-port interrupts dt-bindings: ata: Update ahci bindings with possible per-port interrupts ata: ahci: mvebu: Rename a platform data flag ata: ahci: mvebu: Add a parameter to a platform data callback dt-bindings: ata: Update ahci_mvebu bindings ata: ahci: mvebu: Support A8k compatible ata: ahci: mvebu: Add support for A8k legacy DT bindings irqchip/irq-mvebu-icu: Remove the double SATA ports interrupt hack Thomas Petazzoni (1): arm64: dts: marvell: armada-cp110: Switch to per-port SATA interrupts .../devicetree/bindings/ata/ahci-platform.txt | 7 ++ arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 13 +++- drivers/ata/acard-ahci.c | 2 +- drivers/ata/ahci.c | 8 ++- drivers/ata/ahci.h | 3 +- drivers/ata/ahci_mvebu.c | 61 +++++++++++++--- drivers/ata/libahci.c | 7 +- drivers/ata/libahci_platform.c | 70 ++++++++++++++++--- drivers/ata/sata_highbank.c | 2 +- drivers/irqchip/irq-mvebu-icu.c | 18 ----- include/linux/ahci_platform.h | 1 + 11 files changed, 148 insertions(+), 44 deletions(-)