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Tue, 4 Jun 2019 12:01:52 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 12:01:52 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54H1qr7052476; Tue, 4 Jun 2019 12:01:52 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x54H1pm17287; Tue, 4 Jun 2019 12:01:51 -0500 (CDT) From: Suman Anna To: Jassi Brar , Rob Herring Subject: [PATCH 0/2] Add Mailbox support for TI K3 SoCs Date: Tue, 4 Jun 2019 12:01:44 -0500 Message-ID: <20190604170146.12205-1-s-anna@ti.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190604_100157_928510_A783C819 X-CRM114-Status: GOOD ( 12.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Jassi, The following series adds the support for the Mailbox IP present within the Main NavSS module on the newer TI K3 AM65x and J721E SoCs. The Mailbox IP is similar to the previous generation IP on OMAP SoCs with a few differences: - Multiple IP instances from previous DRA7/AM57 family each form a cluster and are part of the same IP. The driver support will continue to be based on a cluster. - The IP is present within a Main NaVSS, and interrupts have to go through an Interrupt Router within Main NavSS before they reach the respective processor sub-system's interrupt controllers. - The register layout is mostly same, with difference in two registers Support is added by enhancing the existing OMAP Mailbox driver to support the K3 IP using a new compatible. The driver also has to be adjusted to deal with the 32-bit mailbox payloads vs the 64-bit pointers used by the Mailbox API on these Arm v8 platforms. DT nodes will be posted separately once the binding is acked. regards Suman Suman Anna (2): dt-bindings: mailbox: omap: Update bindings for TI K3 SoCs mailbox/omap: Add support for TI K3 SoCs .../bindings/mailbox/omap-mailbox.txt | 59 ++++++++++++++++--- drivers/mailbox/Kconfig | 2 +- drivers/mailbox/omap-mailbox.c | 43 ++++++++------ include/linux/omap-mailbox.h | 4 +- 4 files changed, 80 insertions(+), 28 deletions(-)