From patchwork Tue Aug 6 10:01:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 11078591 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 55B741709 for ; Tue, 6 Aug 2019 10:03:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3FFAE2842A for ; Tue, 6 Aug 2019 10:03:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2D13728900; Tue, 6 Aug 2019 10:03:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9C8DC28968 for ; Tue, 6 Aug 2019 10:03:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=tTGWTm4N6mf+mdIRiDtTsQj0zqNAc+Oyn5PMp5GxByY=; b=sq1/x1pcwg8kOo pPKPnIhWGOk432dyExaT+ir6bOM4GxQ/J0yuuxfrYDmyP9rAQlQWUswMTNFJJY8oH1SszYUzWsH+y 0vuxtAygv3YF67opEFeJZR5y8cdQcA8ZcvyJZbB7evEsKjdAcRpZ4kM1bbpVObYcTZOXannbE0ndG 8GXWMyxt8nHVZi2jXaSgE4PwwoIHU99S9hriyMfDT0+WHFxdXervMZDrdriwFbea+04tZWL4DOUuG Jt6UbP6wgHQ4wSR9DBYENttcSI1Og4CfS5Zrtl6/UK1ctCqixaRSXHPRF3WXIZ7YYx6lRiNDtS2wo lfQOH+wuoc2xkvYkVM3Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1huwJY-0004QU-AS; Tue, 06 Aug 2019 10:03:32 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1huwHc-0002nW-U2 for linux-arm-kernel@lists.infradead.org; Tue, 06 Aug 2019 10:01:35 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 24F33337; Tue, 6 Aug 2019 03:01:28 -0700 (PDT) Received: from filthy-habits.cambridge.arm.com (filthy-habits.cambridge.arm.com [10.1.197.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DF92F3F706; Tue, 6 Aug 2019 03:01:26 -0700 (PDT) From: Marc Zyngier To: Thomas Gleixner , Jason Cooper , Julien Thierry , Rob Herring Subject: [PATCH v2 00/12] irqchip/gic-v3: Add support for GICv3.1 extended PPI/SPI ranges Date: Tue, 6 Aug 2019 11:01:09 +0100 Message-Id: <20190806100121.240767-1-maz@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190806_030133_272261_75789846 X-CRM114-Status: GOOD ( 10.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lokesh Vutla , John Garry , linux-kernel@vger.kernel.org, Shameerali Kolothum Thodi , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Apparently, having ~1000 wired interrupts is not enough, and some people need more. Fear not! The GIC Achitecture Department hereby grants you another 1024 SPIs, together with 64 PPIs, provided that you implement GICv3.1 (see [1] for the details) This series implements the required support, which requires a bit of infrastructure rework in order to make the thing less horrible... This has been tested on a FastModel. If there is no additional issue being reported, I plan to put this into -next toward the end of this week and let it simmer there for a bit. [1] https://developer.arm.com/docs/ihi0069/latest (version E) * From v1: - Tighten ESPI range matching - Added a warning to detect inconsistent distributor/cpu interface configurations - Added quirks to handle HIP06/07 erratum 161010803 which unexpectedly advertise ESPI support Marc Zyngier (12): irqchip/gic: Rework gic_configure_irq to take the full ICFGR base irqchip/gic-v3: Add INTID range and convertion primitives dt-bindings: interrupt-controller: arm,gic-v3: Describe ESPI range support irqchip/gic-v3: Add ESPI range support irqchip/gic: Prepare for more than 16 PPIs irqchip/gic-v3: Dynamically allocate PPI NMI refcounts irqchip/gic-v3: Dynamically allocate PPI partition descriptors dt-bindings: interrupt-controller: arm,gic-v3: Describe EPPI range support irqchip/gic-v3: Add EPPI range support irqchip/gic-v3: Warn about inconsistent implementations of extended ranges irqchip/gic: Skip DT quirks when evaluating IIDR-based quirks irqchip/gic-v3: Add quirks for HIP06/07 invalid GICD_TYPER erratum 161010803 Documentation/arm64/silicon-errata.rst | 2 + .../interrupt-controller/arm,gic-v3.yaml | 6 +- drivers/irqchip/irq-gic-common.c | 35 +- drivers/irqchip/irq-gic-common.h | 2 +- drivers/irqchip/irq-gic-v3.c | 380 ++++++++++++++---- drivers/irqchip/irq-gic.c | 12 +- drivers/irqchip/irq-hip04.c | 9 +- include/linux/irqchip/arm-gic-v3.h | 30 +- 8 files changed, 372 insertions(+), 104 deletions(-)