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[2003:f1:33ce:b00:28ba:a8c7:44a6:f562]) by smtp.googlemail.com with ESMTPSA id c6sm6003120wrb.60.2019.09.21.08.18.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2019 08:18:46 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com Subject: [PATCH 0/6] add the DDR clock controller on Meson8 and Meson8b Date: Sat, 21 Sep 2019 17:18:29 +0200 Message-Id: <20190921151835.770263-1-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190921_081852_648586_DC54D973 X-CRM114-Status: GOOD ( 10.35 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:443 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (martin.blumenstingl[at]googlemail.com) -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Meson8 and Meson8b SoCs embed a DDR clock controller in their MMCBUS registers. This series: - adds support for this DDR clock controller (patches 0 and 1) - wires up the DDR PLL as input for two audio clocks (patches 2 and 3) - adds the DDR clock controller to meson8.dtsi and meson8b.dtsi Special thanks go out to Alexandre Mergnat for switching the Amlogic clock drivers over to parent_hws and parent_data. That made this series a lot easier for me! This series depends on my other series from [0]: "provide the XTAL clock via OF on Meson8/8b/8m2" [0] https://patchwork.kernel.org/cover/11155515/ Martin Blumenstingl (6): dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller clk: meson: meson8b: use of_clk_hw_register to register the clocks clk: meson: meson8b: add the ddr_pll input for the audio clocks ARM: dts: meson8: add the DDR clock controller ARM: dts: meson8b: add the DDR clock controller .../clock/amlogic,meson8-ddr-clkc.yaml | 50 ++++++ arch/arm/boot/dts/meson8.dtsi | 13 +- arch/arm/boot/dts/meson8b.dtsi | 13 +- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/meson8-ddr.c | 153 ++++++++++++++++++ drivers/clk/meson/meson8b.c | 36 ++--- include/dt-bindings/clock/meson8-ddr-clkc.h | 4 + 7 files changed, 245 insertions(+), 26 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml create mode 100644 drivers/clk/meson/meson8-ddr.c create mode 100644 include/dt-bindings/clock/meson8-ddr-clkc.h