From patchwork Fri Oct 25 14:52:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11212507 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4654B112C for ; Fri, 25 Oct 2019 14:52:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 245B521D7F for ; Fri, 25 Oct 2019 14:52:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="hA1QrfPz" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 245B521D7F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=RRIw6T1lsK+/lIiHFr2EGvBlHJF6hwQuvKRkxuaQIkg=; b=hA1QrfPzGgAGq2 Gdgh9X7RtBatgRJImGAYRWyAT03Yd0T+Sx747iRTFrfl73nZhr+CKsjoGbaDDR8Qd+5IXq6x4BVQj cM4SrPtkmjo/JyP4v/xBrJfaUQl2uDCn8A9X5QDP2n08xCilB5pHRrYDX4NNzDfJ8ziRwXfjJzATA hP1d8wjsDkHfpnp/WSEbHH1jU9xc7D+7aWyDAnNKbqf0XLcU830Xm4Yr6kkvSrILse0aXItTvnloR gMenO+32VwtH3yzWfDB6oWdv4zJxAqrhXK9kAVQVydfHcadkis5rsuUf8qkevg+kVAwkTVS8yEl9i tOklsIoeiMqV4dgzkswA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iO0x4-0000uv-LA; Fri, 25 Oct 2019 14:52:30 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iO0x1-0000tz-V0 for linux-arm-kernel@lists.infradead.org; Fri, 25 Oct 2019 14:52:29 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 128AA28; Fri, 25 Oct 2019 07:52:25 -0700 (PDT) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B1CC53F71A; Fri, 25 Oct 2019 07:52:23 -0700 (PDT) From: Andrew Murray To: Catalin Marinas , Will Deacon , Marc Zyngier , Mark Rutland Subject: [PATCH v1 0/3] arm64: perf: Add support for ARMv8.5-PMU 64-bit counters Date: Fri, 25 Oct 2019 15:52:16 +0100 Message-Id: <20191025145219.28350-1-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191025_075228_045419_89FEBC9F X-CRM114-Status: GOOD ( 10.54 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org At present ARMv8 event counters are limited to 32-bits, though by using the CHAIN event it's possible to combine adjacent counters to achieve 64-bits. The perf config1:0 bit can be set to use such a configuration. With the introduction of ARMv8.5-PMU support, all event counters can now be used as 64-bit counters. Let's add support for 64-bit event counters. As KVM doesn't yet support 64-bit event counters, we also trap and emulate the Debug Feature Registers to limit the PMU version a guest sees to PMUv3 for ARMv8.4. Tested by running the following perf command on both guest and host and ensuring that the figures are very similar: perf stat -e armv8_pmuv3/inst_retired,long=1/ \ -e armv8_pmuv3/inst_retired,long=0/ -e cycles Andrew Murray (3): arm64: cpufeature: Extract capped fields KVM: arm64: limit PMU version to ARMv8.4 arm64: perf: Add support for ARMv8.5-PMU 64-bit counters arch/arm64/include/asm/cpufeature.h | 15 +++++ arch/arm64/include/asm/perf_event.h | 3 +- arch/arm64/include/asm/sysreg.h | 4 ++ arch/arm64/kernel/perf_event.c | 86 +++++++++++++++++++++++------ arch/arm64/kvm/sys_regs.c | 36 +++++++++++- include/linux/perf/arm_pmu.h | 1 + 6 files changed, 125 insertions(+), 20 deletions(-)