[v4,00/14] PHY: Add support for SERDES in TI's J721E SoC

Message

Kishon Vijay Abraham I Dec. 16, 2019, 9:56 a.m. UTC

TI's J721E SoC uses Cadence Sierra SERDES for USB, PCIe and SGMII.
TI has a wrapper named WIZ to control input signals to Sierra and
Torrent SERDES.

This patch series:
 1) Add support to WIZ module present in TI's J721E SoC
 2) Adapt Cadence Sierra PHY driver to be used for J721E SoC

Changes from v3:
 *) Fix Rob's comments on dt bindings
        -> Add properties to be added in WIZ child nodes to binding
        -> Use '-' rather than '_' in node names

Changes from v2:
 *) Deprecate "phy_clk" binding
 *) Fix Rob's comment on dt bindings
        -> Include BSD-2-Clause license identifier
        -> drop "oneOf" and "items" for compatible
        -> Fixed "num-lanes" to include only scalar keywords
        -> Change to 32-bit address space for child nodes
*) Rename cmn_refclk/cmn_refclk1 to cmn_refclk_dig_div/
   cmn_refclk1_dig_div

Changes from v1:
 *) Change the dt binding Documentation of WIZ wrapper to YAML format
 *) Fix an issue in Sierra while doimg rmmod

The series has also been pushed to
https://github.com/kishon/linux-wip.git j7_serdes_v4

Anil Varughese (1):
  phy: cadence: Sierra: Configure both lane cdb and common cdb registers
    for external SSC

Kishon Vijay Abraham I (13):
  dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E
  phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional
    resources
  phy: cadence: Sierra: Use "regmap" for read and write to Sierra
    registers
  phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC
  phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops
  phy: cadence: Sierra: Modify register macro names to be in sync with
    Sierra user guide
  phy: cadence: Sierra: Get reset control "array" for each link
  phy: cadence: Sierra: Check for PLL lock during PHY power on
  phy: cadence: Sierra: Change MAX_LANES of Sierra to 16
  phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div
    frequency to 25MHz
  phy: cadence: Sierra: Use correct dev pointer in
    cdns_sierra_phy_remove()
  dt-bindings: phy: Document WIZ (SERDES wrapper) bindings
  phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC

 .../bindings/phy/phy-cadence-sierra.txt       |  13 +-
 .../bindings/phy/ti,phy-j721e-wiz.yaml        | 204 ++++
 drivers/phy/cadence/phy-cadence-sierra.c      | 699 +++++++++++---
 drivers/phy/ti/Kconfig                        |  15 +
 drivers/phy/ti/Makefile                       |   1 +
 drivers/phy/ti/phy-j721e-wiz.c                | 898 ++++++++++++++++++
 6 files changed, 1691 insertions(+), 139 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
 create mode 100644 drivers/phy/ti/phy-j721e-wiz.c

Comments

Kishon Vijay Abraham I Jan. 6, 2020, 6:32 a.m. UTC | #1

On 16/12/19 3:26 PM, Kishon Vijay Abraham I wrote:
> TI's J721E SoC uses Cadence Sierra SERDES for USB, PCIe and SGMII.
> TI has a wrapper named WIZ to control input signals to Sierra and
> Torrent SERDES.

Merged this series.

Thanks
Kishon

> 
> This patch series:
>  1) Add support to WIZ module present in TI's J721E SoC
>  2) Adapt Cadence Sierra PHY driver to be used for J721E SoC
> 
> Changes from v3:
>  *) Fix Rob's comments on dt bindings
>         -> Add properties to be added in WIZ child nodes to binding
>         -> Use '-' rather than '_' in node names
> 
> Changes from v2:
>  *) Deprecate "phy_clk" binding
>  *) Fix Rob's comment on dt bindings
>         -> Include BSD-2-Clause license identifier
>         -> drop "oneOf" and "items" for compatible
>         -> Fixed "num-lanes" to include only scalar keywords
>         -> Change to 32-bit address space for child nodes
> *) Rename cmn_refclk/cmn_refclk1 to cmn_refclk_dig_div/
>    cmn_refclk1_dig_div
> 
> Changes from v1:
>  *) Change the dt binding Documentation of WIZ wrapper to YAML format
>  *) Fix an issue in Sierra while doimg rmmod
> 
> The series has also been pushed to
> https://github.com/kishon/linux-wip.git j7_serdes_v4
> 
> Anil Varughese (1):
>   phy: cadence: Sierra: Configure both lane cdb and common cdb registers
>     for external SSC
> 
> Kishon Vijay Abraham I (13):
>   dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E
>   phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional
>     resources
>   phy: cadence: Sierra: Use "regmap" for read and write to Sierra
>     registers
>   phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC
>   phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops
>   phy: cadence: Sierra: Modify register macro names to be in sync with
>     Sierra user guide
>   phy: cadence: Sierra: Get reset control "array" for each link
>   phy: cadence: Sierra: Check for PLL lock during PHY power on
>   phy: cadence: Sierra: Change MAX_LANES of Sierra to 16
>   phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div
>     frequency to 25MHz
>   phy: cadence: Sierra: Use correct dev pointer in
>     cdns_sierra_phy_remove()
>   dt-bindings: phy: Document WIZ (SERDES wrapper) bindings
>   phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC
> 
>  .../bindings/phy/phy-cadence-sierra.txt       |  13 +-
>  .../bindings/phy/ti,phy-j721e-wiz.yaml        | 204 ++++
>  drivers/phy/cadence/phy-cadence-sierra.c      | 699 +++++++++++---
>  drivers/phy/ti/Kconfig                        |  15 +
>  drivers/phy/ti/Makefile                       |   1 +
>  drivers/phy/ti/phy-j721e-wiz.c                | 898 ++++++++++++++++++
>  6 files changed, 1691 insertions(+), 139 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
>  create mode 100644 drivers/phy/ti/phy-j721e-wiz.c
>