[v5,0/3] arm64: Workaround for Cortex-A55 erratum 1530923

Message ID	20191216115631.17804-1-steven.price@arm.com (mailing list archive)
Headers	show Return-Path: <SRS0=BOSQ=2G=lists.infradead.org=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C15BA206CB From: Steven Price <steven.price@arm.com> To: Catalin Marinas <catalin.marinas@arm.com>, Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org> Subject: [PATCH v5 0/3] arm64: Workaround for Cortex-A55 erratum 1530923 Date: Mon, 16 Dec 2019 11:56:28 +0000 Message-Id: <20191216115631.17804-1-steven.price@arm.com> MIME-Version: 1.0 summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [217.140.110.172 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record Precedence: list Cc: Steven Price <steven.price@arm.com>, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org
Series	arm64: Workaround for Cortex-A55 erratum 1530923 \| expand [v5,0/3] arm64: Workaround for Cortex-A55 erratum 1530923 [v5,1/3] arm64: Rename WORKAROUND_1165522 to SPECULATIVE_AT_VHE [v5,2/3] arm64: Rename WORKAROUND_1319367 to SPECULATIVE_AT_NVHE [v5,3/3] arm64: Workaround for Cortex-A55 erratum 1530923

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20191216115631.17804-1-steven.price@arm.com (mailing list archive)

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DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C15BA206CB
From: Steven Price <steven.price@arm.com>
To: Catalin Marinas <catalin.marinas@arm.com>, Marc Zyngier <maz@kernel.org>,
 Will Deacon <will@kernel.org>
Subject: [PATCH v5 0/3] arm64: Workaround for Cortex-A55 erratum 1530923
Date: Mon, 16 Dec 2019 11:56:28 +0000
Message-Id: <20191216115631.17804-1-steven.price@arm.com>
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Cc: Steven Price <steven.price@arm.com>, linux-kernel@vger.kernel.org,
 linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu
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Series

arm64: Workaround for Cortex-A55 erratum 1530923 | expand

Message

Steven Price Dec. 16, 2019, 11:56 a.m. UTC

Version 5 is a rebasing of version 4 (no changes).

This series enables a workaround for Cortex-A55 erratum 1530923. The
erratum potentially allows TLB entries to be allocated as a result of a
speculative AT instruction. This may happen in the middle of a guest
world switch while the relevant VMSA configuration is in an inconsistent
state, leading to erroneous content being allocated into TLBs.

There are existing workarounds for similar issues, 1165522 is
effectively the same, and 1319367/1319537 is similar but without VHE
support.  Rather than add to the selection of errata, the first patch
renames 1165522 to WORKAROUND_SPECULATIVE_AT which can be reused (in the
final patch) for 1530923.

The workaround for errata 1319367 and 1319537 although similar cannot
use VHE (not available on those CPUs) so cannot share the workaround.
However, to keep some sense of symmetry the workaround is renamed to
SPECULATIVE_AT_NVHE.

Changes since v4:
 * Rebased to v5.5-rc1

Changes since v3:
 * Added Suzuki's reviewed-bys - thanks!
 * Corrected ARM64_WORKAROUND_SPECULATIVE_AT to
   ARM64_WORKAROUND_SPECULATIVE_AT_VHE in the final patch

Changes since v2:
 * Split 1319367/1319537 back into their own workaround, but rename it
   for symmetry with the VHE workaround.

Changes since v1:
 * Combine 1319367/1319537 into the same 'SPECULATIVE_AT' workaround.

Steven Price (3):
  arm64: Rename WORKAROUND_1165522 to SPECULATIVE_AT_VHE
  arm64: Rename WORKAROUND_1319367 to SPECULATIVE_AT_NVHE
  arm64: Workaround for Cortex-A55 erratum 1530923

 Documentation/arm64/silicon-errata.rst |  2 ++
 arch/arm64/Kconfig                     | 21 +++++++++++++++++++++
 arch/arm64/include/asm/cpucaps.h       |  4 ++--
 arch/arm64/include/asm/kvm_host.h      |  2 +-
 arch/arm64/include/asm/kvm_hyp.h       |  6 +++---
 arch/arm64/kernel/cpu_errata.c         | 25 +++++++++++++++++++------
 arch/arm64/kvm/hyp/switch.c            | 10 +++++-----
 arch/arm64/kvm/hyp/sysreg-sr.c         |  4 ++--
 arch/arm64/kvm/hyp/tlb.c               | 12 ++++++------
 9 files changed, 61 insertions(+), 25 deletions(-)

Comments

Will Deacon Jan. 14, 2020, 4:45 p.m. UTC | #1

On Mon, Dec 16, 2019 at 11:56:28AM +0000, Steven Price wrote:
> Version 5 is a rebasing of version 4 (no changes).
> 
> This series enables a workaround for Cortex-A55 erratum 1530923. The
> erratum potentially allows TLB entries to be allocated as a result of a
> speculative AT instruction. This may happen in the middle of a guest
> world switch while the relevant VMSA configuration is in an inconsistent
> state, leading to erroneous content being allocated into TLBs.
> 
> There are existing workarounds for similar issues, 1165522 is
> effectively the same, and 1319367/1319537 is similar but without VHE
> support.  Rather than add to the selection of errata, the first patch
> renames 1165522 to WORKAROUND_SPECULATIVE_AT which can be reused (in the
> final patch) for 1530923.
> 
> The workaround for errata 1319367 and 1319537 although similar cannot
> use VHE (not available on those CPUs) so cannot share the workaround.
> However, to keep some sense of symmetry the workaround is renamed to
> SPECULATIVE_AT_NVHE.
> 
> Changes since v4:
>  * Rebased to v5.5-rc1

Looks fine to me. Marc, are you ok with me queueing this via arm64 (that's
where the existing workarounds came from), or would you prefer to take them
via kvm-arm?

Will

Marc Zyngier Jan. 16, 2020, 7:28 a.m. UTC | #2

On 2020-01-14 16:45, Will Deacon wrote:
> On Mon, Dec 16, 2019 at 11:56:28AM +0000, Steven Price wrote:
>> Version 5 is a rebasing of version 4 (no changes).
>> 
>> This series enables a workaround for Cortex-A55 erratum 1530923. The
>> erratum potentially allows TLB entries to be allocated as a result of 
>> a
>> speculative AT instruction. This may happen in the middle of a guest
>> world switch while the relevant VMSA configuration is in an 
>> inconsistent
>> state, leading to erroneous content being allocated into TLBs.
>> 
>> There are existing workarounds for similar issues, 1165522 is
>> effectively the same, and 1319367/1319537 is similar but without VHE
>> support.  Rather than add to the selection of errata, the first patch
>> renames 1165522 to WORKAROUND_SPECULATIVE_AT which can be reused (in 
>> the
>> final patch) for 1530923.
>> 
>> The workaround for errata 1319367 and 1319537 although similar cannot
>> use VHE (not available on those CPUs) so cannot share the workaround.
>> However, to keep some sense of symmetry the workaround is renamed to
>> SPECULATIVE_AT_NVHE.
>> 
>> Changes since v4:
>>  * Rebased to v5.5-rc1
> 
> Looks fine to me. Marc, are you ok with me queueing this via arm64 
> (that's
> where the existing workarounds came from), or would you prefer to take 
> them
> via kvm-arm?

Please go ahead and take it (with my ack) via the arm64 tree.

Thanks,

        M.

Will Deacon Jan. 16, 2020, 10:47 a.m. UTC | #3

On Thu, Jan 16, 2020 at 07:28:49AM +0000, Marc Zyngier wrote:
> On 2020-01-14 16:45, Will Deacon wrote:
> > On Mon, Dec 16, 2019 at 11:56:28AM +0000, Steven Price wrote:
> > > Version 5 is a rebasing of version 4 (no changes).
> > > 
> > > This series enables a workaround for Cortex-A55 erratum 1530923. The
> > > erratum potentially allows TLB entries to be allocated as a result
> > > of a
> > > speculative AT instruction. This may happen in the middle of a guest
> > > world switch while the relevant VMSA configuration is in an
> > > inconsistent
> > > state, leading to erroneous content being allocated into TLBs.
> > > 
> > > There are existing workarounds for similar issues, 1165522 is
> > > effectively the same, and 1319367/1319537 is similar but without VHE
> > > support.  Rather than add to the selection of errata, the first patch
> > > renames 1165522 to WORKAROUND_SPECULATIVE_AT which can be reused (in
> > > the
> > > final patch) for 1530923.
> > > 
> > > The workaround for errata 1319367 and 1319537 although similar cannot
> > > use VHE (not available on those CPUs) so cannot share the workaround.
> > > However, to keep some sense of symmetry the workaround is renamed to
> > > SPECULATIVE_AT_NVHE.
> > > 
> > > Changes since v4:
> > >  * Rebased to v5.5-rc1
> > 
> > Looks fine to me. Marc, are you ok with me queueing this via arm64
> > (that's
> > where the existing workarounds came from), or would you prefer to take
> > them
> > via kvm-arm?
> 
> Please go ahead and take it (with my ack) via the arm64 tree.

Will do, thanks!

Will