[0/7] ti-sysc driver fix for hdq1w and few improvments

Message

Tony Lindgren Feb. 21, 2020, 7:52 p.m. UTC

Hi all,

Here are some ti-sysc interconnect target module driver fixes and
improvments.

There's a fix for 1-wire reset, the rest can wait for v5.7 merge
window.

Regards,

Tony



Tony Lindgren (7):
  bus: ti-sysc: Fix 1-wire reset quirk
  bus: ti-sysc: Rename clk related quirks to pre_reset and post_reset
    quirks
  ti-sysc: Improve reset to work with modules with no sysconfig
  bus: ti-sysc: Consider non-existing registers too when matching quirks
  bus: ti-sysc: Don't warn about legacy property for nested ti-sysc
    devices
  bus: ti-sysc: Implement SoC revision handling
  bus: ti-sysc: Handle module unlock quirk needed for some RTC

 arch/arm/mach-omap2/pdata-quirks.c    |   6 +
 drivers/bus/ti-sysc.c                 | 430 ++++++++++++++++++++------
 include/linux/platform_data/ti-sysc.h |   2 +
 3 files changed, 348 insertions(+), 90 deletions(-)