[RFC,V6,0/3] media: support Mediatek sensor interface driver

Message ID	20200410071723.19720-1-louis.kuo@mediatek.com (mailing list archive)
Headers	show Return-Path: <SRS0=tIb0=52=lists.infradead.org=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A2B9A2087E From: Louis Kuo <louis.kuo@mediatek.com> To: <hans.verkuil@cisco.com>, <laurent.pinchart+renesas@ideasonboard.com>, <tfiga@chromium.org>, <keiichiw@chromium.org>, <matthias.bgg@gmail.com>, <mchehab@kernel.org> Subject: [RFC PATCH V6 0/3] media: support Mediatek sensor interface driver Date: Fri, 10 Apr 2020 15:17:20 +0800 Message-ID: <20200410071723.19720-1-louis.kuo@mediatek.com> MIME-Version: 1.0 summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [216.200.240.184 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines Precedence: list Cc: devicetree@vger.kernel.org, Sean.Cheng@mediatek.com, srv_heupstream@mediatek.com, Jerry-ch.Chen@mediatek.com, jungo.lin@mediatek.com, sj.huang@mediatek.com, yuzhao@chromium.org, linux-mediatek@lists.infradead.org, zwisler@chromium.org, louis.kuo@mediatek.com, christie.yu@mediatek.com, frederic.chen@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org
Series	media: support Mediatek sensor interface driver \| expand [RFC,V6,0/3] media: support Mediatek sensor interface driver [RFC,V6,2/3] dt-bindings: mt8183: Add sensor interface dt-bindings [RFC,V6,3/3] dts: arm64: mt8183: Add sensor interface nodes

Louis Kuo April 10, 2020, 7:17 a.m. UTC

Hello,

This is the RFC patch adding Sensor Inferface(seninf) driver on Mediatek mt8183 SoC, which will be used
in camera features on CrOS application.
It belongs to the first Mediatek's camera driver series based on V4L2 and media controller framework.
I posted the main part of the seninf driver as RFC to discuss first and would like some review comments
on the overall structure of the driver.

The driver is implemented with V4L2 framework.
1. Register as a V4L2 sub-device.
2. Only one entity with sink pads linked to camera sensors for choosing desired camera sensor by setup link
   and with source pads linked to cam-io for routing different types of decoded packet datas to PASS1 driver
   to generate sensor image frame and meta-data.

The overall file structure of the seninf driver is as following:

* mtk_seninf.c: Implement software and HW control flow of seninf driver.
* mtk_seninf_reg.h: Define HW register R/W macros and HW register names.
* mtk_seninf_rx_reg.h: Define HW RX register R/W macros and HW register names.

[ V6: Change parse endpoints API, fix coding style, refine error handling and return value,
remove redundant macros and header files]

  media: platform: mtk-isp: Add Mediatek sensor interface driver
  dt-bindings: mt8183: Add sensor interface dt-bindings
  dts: arm64: mt8183: Add sensor interface nodes

 .../bindings/media/mediatek-seninf.yaml       |  219 +++
 arch/arm64/boot/dts/mediatek/mt8183.dtsi      |   25 +
 drivers/media/platform/Makefile               |    1 +
 drivers/media/platform/mtk-isp/Kconfig        |   18 +
 drivers/media/platform/mtk-isp/Makefile       |    3 +
 .../media/platform/mtk-isp/seninf/Makefile    |    5 +
 drivers/media/platform/mtk-isp/seninf/TODO    |   18 +
 .../platform/mtk-isp/seninf/mtk_seninf.c      | 1173 +++++++++++++
 .../platform/mtk-isp/seninf/mtk_seninf_reg.h  | 1491 +++++++++++++++++
 .../mtk-isp/seninf/mtk_seninf_rx_reg.h        | 1398 ++++++++++++++++
 10 files changed, 4351 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/mediatek-seninf.yaml
 create mode 100644 drivers/media/platform/mtk-isp/Kconfig
 create mode 100644 drivers/media/platform/mtk-isp/Makefile
 create mode 100644 drivers/media/platform/mtk-isp/seninf/Makefile
 create mode 100644 drivers/media/platform/mtk-isp/seninf/TODO
 create mode 100644 drivers/media/platform/mtk-isp/seninf/mtk_seninf.c
 create mode 100644 drivers/media/platform/mtk-isp/seninf/mtk_seninf_reg.h
 create mode 100644 drivers/media/platform/mtk-isp/seninf/mtk_seninf_rx_reg.h

Chun-Kuang Hu April 11, 2020, 12:16 a.m. UTC | #1

Hi, Louis:

Louis Kuo <louis.kuo@mediatek.com> 於 2020年4月10日 週五 下午3:18寫道：
>
> This patch adds Mediatek's sensor interface driver. Sensor interface driver
> is a MIPI-CSI2 host driver, namely, a HW camera interface controller. It
> support a widely adopted, simple, high-speed protocol primarily intended for
> point-to-point image and video transmission between cameras and host
> devices. The mtk-isp directory will contain drivers for multiple IP blocks
> found in Mediatek ISP system. It will include ISP Pass 1 driver, sensor interface
> driver, DIP driver and face detection driver.
>
> Signed-off-by: Louis Kuo <louis.kuo@mediatek.com>
> ---
>  drivers/media/platform/Makefile               |    1 +
>  drivers/media/platform/mtk-isp/Kconfig        |   18 +
>  drivers/media/platform/mtk-isp/Makefile       |    3 +
>  .../media/platform/mtk-isp/seninf/Makefile    |    5 +
>  drivers/media/platform/mtk-isp/seninf/TODO    |   18 +
>  .../platform/mtk-isp/seninf/mtk_seninf.c      | 1173 +++++++++++++
>  .../platform/mtk-isp/seninf/mtk_seninf_reg.h  | 1491 +++++++++++++++++
>  .../mtk-isp/seninf/mtk_seninf_rx_reg.h        | 1398 ++++++++++++++++
>  8 files changed, 4107 insertions(+)
>  create mode 100644 drivers/media/platform/mtk-isp/Kconfig
>  create mode 100644 drivers/media/platform/mtk-isp/Makefile
>  create mode 100644 drivers/media/platform/mtk-isp/seninf/Makefile
>  create mode 100644 drivers/media/platform/mtk-isp/seninf/TODO
>  create mode 100644 drivers/media/platform/mtk-isp/seninf/mtk_seninf.c
>  create mode 100644 drivers/media/platform/mtk-isp/seninf/mtk_seninf_reg.h
>  create mode 100644 drivers/media/platform/mtk-isp/seninf/mtk_seninf_rx_reg.h
>

[snip]

> +
> +static void mtk_seninf_set_dphy(struct mtk_seninf *priv, unsigned int seninf)
> +{
> +       void __iomem *pmipi_rx_base = priv->csi2_rx[CFG_CSI_PORT_0];
> +       unsigned int port = priv->port;
> +       void __iomem *pmipi_rx = priv->csi2_rx[port];
> +       void __iomem *pmipi_rx_conf = priv->base + 0x1000 * seninf;
> +
> +       /* Set analog phy mode to DPHY */
> +       if (is_cdphy_combo(port))
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A, RG_CSI0A_CPHY_EN, 0);
> +       /* 4D1C: MIPIRX_ANALOG_A_BASE = 0x00001A42 */
> +       if (is_4d1c(port)) {
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> +                           RG_CSI0A_DPHY_L0_CKMODE_EN, 0);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> +                           RG_CSI0A_DPHY_L0_CKSEL, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> +                           RG_CSI0A_DPHY_L1_CKMODE_EN, 0);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> +                           RG_CSI0A_DPHY_L1_CKSEL, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> +                           RG_CSI0A_DPHY_L2_CKMODE_EN, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> +                           RG_CSI0A_DPHY_L2_CKSEL, 1);
> +       } else {/* MIPIRX_ANALOG_BASE = 0x102 */
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> +                           RG_CSI0A_DPHY_L0_CKMODE_EN, 0);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> +                           RG_CSI0A_DPHY_L0_CKSEL, 0);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> +                           RG_CSI0A_DPHY_L1_CKMODE_EN, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> +                           RG_CSI0A_DPHY_L1_CKSEL, 0);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> +                           RG_CSI0A_DPHY_L2_CKMODE_EN, 0);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> +                           RG_CSI0A_DPHY_L2_CKSEL, 0);
> +       }
> +       if (is_cdphy_combo(port))
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B, RG_CSI0B_CPHY_EN, 0);
> +
> +       /* Only 4d1c need set CSIB: MIPIRX_ANALOG_B_BASE = 0x00001242 */
> +       if (is_4d1c(port)) {
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> +                           RG_CSI0B_DPHY_L0_CKMODE_EN, 0);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> +                           RG_CSI0B_DPHY_L0_CKSEL, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> +                           RG_CSI0B_DPHY_L1_CKMODE_EN, 0);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> +                           RG_CSI0B_DPHY_L1_CKSEL, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> +                           RG_CSI0B_DPHY_L2_CKMODE_EN, 0);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> +                           RG_CSI0B_DPHY_L2_CKSEL, 1);
> +       } else {/* MIPIRX_ANALOG_BASE = 0x102 */
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> +                           RG_CSI0B_DPHY_L0_CKSEL, 0);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> +                           RG_CSI0B_DPHY_L1_CKMODE_EN, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> +                           RG_CSI0B_DPHY_L1_CKSEL, 0);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> +                           RG_CSI0B_DPHY_L2_CKMODE_EN, 0);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> +                           RG_CSI0B_DPHY_L2_CKSEL, 0);
> +       }
> +       /* Byte clock invert */
> +       SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0A,
> +                   RG_CSI0A_CDPHY_L0_T0_BYTECK_INVERT, 1);
> +       SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0A,
> +                   RG_CSI0A_DPHY_L1_BYTECK_INVERT, 1);
> +       SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0A,
> +                   RG_CSI0A_CDPHY_L2_T1_BYTECK_INVERT, 1);
> +
> +       if (is_4d1c(port)) {
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0B,
> +                           RG_CSI0B_CDPHY_L0_T0_BYTECK_INVERT, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0B,
> +                           RG_CSI0B_DPHY_L1_BYTECK_INVERT, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0B,
> +                           RG_CSI0B_CDPHY_L2_T1_BYTECK_INVERT, 1);
> +       }
> +
> +       /* Start ANA EQ tuning */
> +       if (is_cdphy_combo(port)) {
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0A,
> +                           RG_CSI0A_L0_T0AB_EQ_IS, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0A,
> +                           RG_CSI0A_L0_T0AB_EQ_BW, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0A,
> +                           RG_CSI0A_L1_T1AB_EQ_IS, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0A,
> +                           RG_CSI0A_L1_T1AB_EQ_BW, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0A,
> +                           RG_CSI0A_L2_T1BC_EQ_IS, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0A,
> +                           RG_CSI0A_L2_T1BC_EQ_BW, 1);
> +
> +               if (is_4d1c(port)) { /* 4d1c */
> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0B,
> +                                   RG_CSI0B_L0_T0AB_EQ_IS, 1);
> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0B,
> +                                   RG_CSI0B_L0_T0AB_EQ_BW, 1);
> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0B,
> +                                   RG_CSI0B_L1_T1AB_EQ_IS, 1);
> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0B,
> +                                   RG_CSI0B_L1_T1AB_EQ_BW, 1);
> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0B,
> +                                   RG_CSI0B_L2_T1BC_EQ_IS, 1);
> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0B,
> +                                   RG_CSI0B_L2_T1BC_EQ_BW, 1);
> +               }
> +       } else {
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
> +                           RG_CSI1A_L0_EQ_IS, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
> +                           RG_CSI1A_L0_EQ_BW, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
> +                           RG_CSI1A_L1_EQ_IS, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
> +                           RG_CSI1A_L1_EQ_BW, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1A,
> +                           RG_CSI1A_L2_EQ_IS, 1);
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1A,
> +                           RG_CSI1A_L2_EQ_BW, 1);
> +
> +               if (is_4d1c(port)) { /* 4d1c */
> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
> +                                   RG_CSI1B_L0_EQ_IS, 1);
> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
> +                                   RG_CSI1B_L0_EQ_BW, 1);
> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
> +                                   RG_CSI1B_L1_EQ_IS, 1);
> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
> +                                   RG_CSI1B_L1_EQ_BW, 1);
> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1B,
> +                                   RG_CSI1B_L2_EQ_IS, 1);
> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1B,
> +                                   RG_CSI1B_L2_EQ_BW, 1);
> +               }
> +       }
> +
> +       /* End ANA EQ tuning */
> +       writel(0x90, pmipi_rx_base + MIPI_RX_ANA40_CSI0A);
> +       SENINF_BITS(pmipi_rx, MIPI_RX_ANA24_CSI0A,
> +                   RG_CSI0A_RESERVE, 0x40);
> +       if (is_4d1c(port))
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA24_CSI0B,
> +                           RG_CSI0B_RESERVE, 0x40);
> +       SENINF_BITS(pmipi_rx, MIPI_RX_WRAPPER80_CSI0A,
> +                   CSR_CSI_RST_MODE, 0);
> +       if (is_4d1c(port))
> +               SENINF_BITS(pmipi_rx, MIPI_RX_WRAPPER80_CSI0B,
> +                           CSR_CSI_RST_MODE, 0);
> +       /* ANA power on */
> +       SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> +                   RG_CSI0A_BG_CORE_EN, 1);
> +       if (is_4d1c(port))
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> +                           RG_CSI0B_BG_CORE_EN, 1);
> +       usleep_range(20, 40);
> +       SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> +                   RG_CSI0A_BG_LPF_EN, 1);
> +       if (is_4d1c(port))
> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> +                           RG_CSI0B_BG_LPF_EN, 1);
> +
> +       udelay(1);
> +       /* 4d1c: MIPIRX_CONFIG_CSI_BASE = 0xC9000000; */
> +       if (is_4d1c(port)) {
> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> +                           CSI0_BIST_LN0_MUX, 1);
> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> +                           CSI0_BIST_LN1_MUX, 2);
> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> +                           CSI0_BIST_LN2_MUX, 0);
> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> +                           CSI0_BIST_LN3_MUX, 3);
> +       } else { /* 2d1c: MIPIRX_CONFIG_CSI_BASE = 0xE4000000; */
> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> +                           CSI0_BIST_LN0_MUX, 0);
> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> +                           CSI0_BIST_LN1_MUX, 1);
> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> +                           CSI0_BIST_LN2_MUX, 2);
> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> +                           CSI0_BIST_LN3_MUX, 3);
> +       }
> +}

I think the phy control part should be placed in
drivers/phy/mediatek/. In [1], device csis point to a device mipi_phy.
csis' driver is in [2], and mipi_phy's driver is in [3]

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/exynos4.dtsi?h=v5.6
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/media/platform/exynos4-is/mipi-csis.c?h=v5.6
[3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/phy/samsung/phy-exynos-mipi-video.c?h=v5.6

Regards,
Chun-Kuang.

Chun-Kuang Hu April 11, 2020, 10:25 a.m. UTC | #2

Hi, Louis:

Louis Kuo <louis.kuo@mediatek.com> 於 2020年4月10日 週五 下午3:18寫道：
>
> This patch adds Mediatek's sensor interface driver. Sensor interface driver
> is a MIPI-CSI2 host driver, namely, a HW camera interface controller. It
> support a widely adopted, simple, high-speed protocol primarily intended for
> point-to-point image and video transmission between cameras and host
> devices. The mtk-isp directory will contain drivers for multiple IP blocks
> found in Mediatek ISP system. It will include ISP Pass 1 driver, sensor interface
> driver, DIP driver and face detection driver.
>
> Signed-off-by: Louis Kuo <louis.kuo@mediatek.com>
> ---
>  drivers/media/platform/Makefile               |    1 +
>  drivers/media/platform/mtk-isp/Kconfig        |   18 +
>  drivers/media/platform/mtk-isp/Makefile       |    3 +
>  .../media/platform/mtk-isp/seninf/Makefile    |    5 +
>  drivers/media/platform/mtk-isp/seninf/TODO    |   18 +
>  .../platform/mtk-isp/seninf/mtk_seninf.c      | 1173 +++++++++++++
>  .../platform/mtk-isp/seninf/mtk_seninf_reg.h  | 1491 +++++++++++++++++
>  .../mtk-isp/seninf/mtk_seninf_rx_reg.h        | 1398 ++++++++++++++++
>  8 files changed, 4107 insertions(+)
>  create mode 100644 drivers/media/platform/mtk-isp/Kconfig
>  create mode 100644 drivers/media/platform/mtk-isp/Makefile
>  create mode 100644 drivers/media/platform/mtk-isp/seninf/Makefile
>  create mode 100644 drivers/media/platform/mtk-isp/seninf/TODO
>  create mode 100644 drivers/media/platform/mtk-isp/seninf/mtk_seninf.c
>  create mode 100644 drivers/media/platform/mtk-isp/seninf/mtk_seninf_reg.h
>  create mode 100644 drivers/media/platform/mtk-isp/seninf/mtk_seninf_rx_reg.h
>

[snip]

> diff --git a/drivers/media/platform/mtk-isp/seninf/mtk_seninf_rx_reg.h b/drivers/media/platform/mtk-isp/seninf/mtk_seninf_rx_reg.h
> new file mode 100644
> index 000000000000..7e7c68853e11
> --- /dev/null
> +++ b/drivers/media/platform/mtk-isp/seninf/mtk_seninf_rx_reg.h
> @@ -0,0 +1,1398 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
> +#ifndef __SENINF_RX_REG_H__
> +#define __SENINF_RX_REG_H__
> +
> +#define BIT(nr) (1UL << (nr))

This has been defined in bits.h

> +
> +#define MIPI_RX_ANA00_CSI0A                                    0x0000
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_CPHY_EN_SHIFT 0
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_CPHY_EN_MASK BIT(0)
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_EQ_PROTECT_EN_SHIFT 1
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_EQ_PROTECT_EN_MASK BIT(1)
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_BG_LPF_EN_SHIFT 2
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_BG_LPF_EN_MASK BIT(2)
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_BG_CORE_EN_SHIFT 3
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_BG_CORE_EN_MASK BIT(3)
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_DPHY_L0_CKMODE_EN_SHIFT 5
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_DPHY_L0_CKMODE_EN_MASK BIT(5)
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_DPHY_L0_CKSEL_SHIFT 6
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_DPHY_L0_CKSEL_MASK BIT(6)
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_DPHY_L1_CKMODE_EN_SHIFT 8
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_DPHY_L1_CKMODE_EN_MASK BIT(8)
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_DPHY_L1_CKSEL_SHIFT 9
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_DPHY_L1_CKSEL_MASK BIT(9)
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_DPHY_L2_CKMODE_EN_SHIFT 11
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_DPHY_L2_CKMODE_EN_MASK BIT(11)
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_DPHY_L2_CKSEL_SHIFT 12
> +#define MIPI_RX_ANA00_CSI0A_RG_CSI0A_DPHY_L2_CKSEL_MASK BIT(12)
> +#define MIPI_RX_ANA04_CSI0A                                    0x0004
> +#define MIPI_RX_ANA04_CSI0A_RG_CSI0A_BG_LPRX_VTH_SEL_SHIFT 0
> +#define MIPI_RX_ANA04_CSI0A_RG_CSI0A_BG_LPRX_VTH_SEL_MASK (0x7 << 0)
> +#define MIPI_RX_ANA04_CSI0A_RG_CSI0A_BG_LPRX_VTL_SEL_SHIFT 4
> +#define MIPI_RX_ANA04_CSI0A_RG_CSI0A_BG_LPRX_VTL_SEL_MASK (0x7 << 4)
> +#define MIPI_RX_ANA04_CSI0A_RG_CSI0A_BG_HSDET_VTH_SEL_SHIFT 8
> +#define MIPI_RX_ANA04_CSI0A_RG_CSI0A_BG_HSDET_VTH_SEL_MASK (0x7 << 8)
> +#define MIPI_RX_ANA04_CSI0A_RG_CSI0A_BG_HSDET_VTL_SEL_SHIFT 12
> +#define MIPI_RX_ANA04_CSI0A_RG_CSI0A_BG_HSDET_VTL_SEL_MASK (0x7 << 12)
> +#define MIPI_RX_ANA04_CSI0A_RG_CSI0A_BG_VREF_SEL_SHIFT 16
> +#define MIPI_RX_ANA04_CSI0A_RG_CSI0A_BG_VREF_SEL_MASK (0xf << 16)
> +#define MIPI_RX_ANA04_CSI0A_RG_CSI0A_BG_MON_VREF_SEL_SHIFT 24
> +#define MIPI_RX_ANA04_CSI0A_RG_CSI0A_BG_MON_VREF_SEL_MASK (0xf << 24)
> +#define MIPI_RX_ANA04_CSI0A_RG_CSI0A_FORCE_HSRT_EN_SHIFT 28
> +#define MIPI_RX_ANA04_CSI0A_RG_CSI0A_FORCE_HSRT_EN_MASK BIT(28)
> +#define MIPI_RX_ANA08_CSI0A                                    0x0008
> +#define MIPI_RX_ANA08_CSI0A_RG_CSI0A_L0P_T0A_HSRT_CODE_SHIFT 0
> +#define MIPI_RX_ANA08_CSI0A_RG_CSI0A_L0P_T0A_HSRT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA08_CSI0A_RG_CSI0A_L0N_T0B_HSRT_CODE_SHIFT 8
> +#define MIPI_RX_ANA08_CSI0A_RG_CSI0A_L0N_T0B_HSRT_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA08_CSI0A_RG_CSI0A_L1P_T0C_HSRT_CODE_SHIFT 16
> +#define MIPI_RX_ANA08_CSI0A_RG_CSI0A_L1P_T0C_HSRT_CODE_MASK (0x1f << 16)
> +#define MIPI_RX_ANA08_CSI0A_RG_CSI0A_L1N_T1A_HSRT_CODE_SHIFT 24
> +#define MIPI_RX_ANA08_CSI0A_RG_CSI0A_L1N_T1A_HSRT_CODE_MASK (0x1f << 24)
> +#define MIPI_RX_ANA0C_CSI0A                                    0x000C
> +#define MIPI_RX_ANA0C_CSI0A_RG_CSI0A_L2P_T1B_HSRT_CODE_SHIFT 0
> +#define MIPI_RX_ANA0C_CSI0A_RG_CSI0A_L2P_T1B_HSRT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA0C_CSI0A_RG_CSI0A_L2N_T1C_HSRT_CODE_SHIFT 8
> +#define MIPI_RX_ANA0C_CSI0A_RG_CSI0A_L2N_T1C_HSRT_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA10_CSI0A                                    0x0010
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L0_DELAYCAL_EN_SHIFT 0
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L0_DELAYCAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L0_DELAYCAL_RSTB_SHIFT 1
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L0_DELAYCAL_RSTB_MASK BIT(1)
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L0_VREF_SEL_SHIFT 2
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L0_VREF_SEL_MASK (0x3f << 2)
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L1_DELAYCAL_EN_SHIFT 8
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L1_DELAYCAL_EN_MASK BIT(8)
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L1_DELAYCAL_RSTB_SHIFT 9
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L1_DELAYCAL_RSTB_MASK BIT(9)
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L1_VREF_SEL_SHIFT 10
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L1_VREF_SEL_MASK (0x3f << 10)
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L2_DELAYCAL_EN_SHIFT 16
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L2_DELAYCAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L2_DELAYCAL_RSTB_SHIFT 17
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L2_DELAYCAL_RSTB_MASK BIT(17)
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L2_VREF_SEL_SHIFT 18
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_DPHY_L2_VREF_SEL_MASK (0x3f << 18)
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_CPHY_T0_CDR_DELAYCAL_EN_SHIFT 24
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_CPHY_T0_CDR_DELAYCAL_EN_MASK BIT(24)
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_CPHY_T0_CDR_DELAYCAL_RSTB_SHIFT 25
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_CPHY_T0_CDR_DELAYCAL_RSTB_MASK BIT(25)
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_CPHY_T0_VREF_SEL_SHIFT 26
> +#define MIPI_RX_ANA10_CSI0A_RG_CSI0A_CPHY_T0_VREF_SEL_MASK (0x3f << 26)
> +#define MIPI_RX_ANA14_CSI0A                                    0x0014
> +#define MIPI_RX_ANA14_CSI0A_RG_CSI0A_CPHY_T1_CDR_DELAYCAL_EN_SHIFT 0
> +#define MIPI_RX_ANA14_CSI0A_RG_CSI0A_CPHY_T1_CDR_DELAYCAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA14_CSI0A_RG_CSI0A_CPHY_T1_CDR_DELAYCAL_RSTB_SHIFT 1
> +#define MIPI_RX_ANA14_CSI0A_RG_CSI0A_CPHY_T1_CDR_DELAYCAL_RSTB_MASK BIT(1)
> +#define MIPI_RX_ANA14_CSI0A_RG_CSI0A_CPHY_T1_VREF_SEL_SHIFT 2
> +#define MIPI_RX_ANA14_CSI0A_RG_CSI0A_CPHY_T1_VREF_SEL_MASK (0x3f << 2)
> +#define MIPI_RX_ANA18_CSI0A                                    0x0018
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_OS_CAL_EN_SHIFT 0
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_OS_CAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_MON_EN_SHIFT 1
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_MON_EN_MASK BIT(1)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_SCA_SHIFT 2
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_SCA_MASK BIT(2)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_SCB_SHIFT 3
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_SCB_MASK BIT(3)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_IS_SHIFT 4
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_IS_MASK (0x3 << 4)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_BW_SHIFT 6
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_BW_MASK (0x3 << 6)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_SRA_SHIFT 8
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_SRA_MASK (0xf << 8)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_SRB_SHIFT 12
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_L0_T0AB_EQ_SRB_MASK (0xf << 12)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_OS_CAL_EN_SHIFT 16
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_OS_CAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_MON_EN_SHIFT 17
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_MON_EN_MASK BIT(17)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_SCA_SHIFT 18
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_SCA_MASK BIT(18)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_SCB_SHIFT 19
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_SCB_MASK BIT(19)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_IS_SHIFT 20
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_IS_MASK (0x3 << 20)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_BW_SHIFT 22
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_BW_MASK (0x3 << 22)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_SRA_SHIFT 24
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_SRA_MASK (0xf << 24)
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_SRB_SHIFT 28
> +#define MIPI_RX_ANA18_CSI0A_RG_CSI0A_XX_T0CA_EQ_SRB_MASK (0xf << 28)
> +#define MIPI_RX_ANA1C_CSI0A                                    0x001C
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_OS_CAL_EN_SHIFT 0
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_OS_CAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_MON_EN_SHIFT 1
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_MON_EN_MASK BIT(1)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_SCA_SHIFT 2
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_SCA_MASK BIT(2)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_SCB_SHIFT 3
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_SCB_MASK BIT(3)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_IS_SHIFT 4
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_IS_MASK (0x3 << 4)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_BW_SHIFT 6
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_BW_MASK (0x3 << 6)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_SRA_SHIFT 8
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_SRA_MASK (0xf << 8)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_SRB_SHIFT 12
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_XX_T0BC_EQ_SRB_MASK (0xf << 12)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_OS_CAL_EN_SHIFT 16
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_OS_CAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_MON_EN_SHIFT 17
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_MON_EN_MASK BIT(17)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_SCA_SHIFT 18
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_SCA_MASK BIT(18)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_SCB_SHIFT 19
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_SCB_MASK BIT(19)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_IS_SHIFT 20
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_IS_MASK (0x3 << 20)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_BW_SHIFT 22
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_BW_MASK (0x3 << 22)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_SRA_SHIFT 24
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_SRA_MASK (0xf << 24)
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_SRB_SHIFT 28
> +#define MIPI_RX_ANA1C_CSI0A_RG_CSI0A_L1_T1AB_EQ_SRB_MASK (0xf << 28)
> +#define MIPI_RX_ANA20_CSI0A                                    0x0020
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_OS_CAL_EN_SHIFT 0
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_OS_CAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_MON_EN_SHIFT 1
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_MON_EN_MASK BIT(1)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_SCA_SHIFT 2
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_SCA_MASK BIT(2)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_SCB_SHIFT 3
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_SCB_MASK BIT(3)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_IS_SHIFT 4
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_IS_MASK (0x3 << 4)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_BW_SHIFT 6
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_BW_MASK (0x3 << 6)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_SRA_SHIFT 8
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_SRA_MASK (0xf << 8)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_SRB_SHIFT 12
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_XX_T1CA_EQ_SRB_MASK (0xf << 12)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_OS_CAL_EN_SHIFT 16
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_OS_CAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_MON_EN_SHIFT 17
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_MON_EN_MASK BIT(17)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_SCA_SHIFT 18
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_SCA_MASK BIT(18)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_SCB_SHIFT 19
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_SCB_MASK BIT(19)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_IS_SHIFT 20
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_IS_MASK (0x3 << 20)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_BW_SHIFT 22
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_BW_MASK (0x3 << 22)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_SRA_SHIFT 24
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_SRA_MASK (0xf << 24)
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_SRB_SHIFT 28
> +#define MIPI_RX_ANA20_CSI0A_RG_CSI0A_L2_T1BC_EQ_SRB_MASK (0xf << 28)
> +#define MIPI_RX_ANA24_CSI0A                                    0x0024
> +#define MIPI_RX_ANA24_CSI0A_RG_CSI0A_RESERVE_SHIFT 24
> +#define MIPI_RX_ANA24_CSI0A_RG_CSI0A_RESERVE_MASK (0xff << 24)
> +#define MIPI_RX_ANA28_CSI0A                                    0x0028
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_DIRECT_EN_SHIFT 0
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_DIRECT_EN_MASK BIT(0)
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_AUTOLOAD_EN_SHIFT 1
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_AUTOLOAD_EN_MASK BIT(1)
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_LPF_CTRL_SHIFT 2
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_LPF_CTRL_MASK (0x3 << 2)
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_AB_WIDTH_SHIFT 4
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_AB_WIDTH_MASK (0xf << 4)
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_BC_WIDTH_SHIFT 8
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_BC_WIDTH_MASK (0xf << 8)
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_CA_WIDTH_SHIFT 12
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_CA_WIDTH_MASK (0xf << 12)
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_CK_DELAY_SHIFT 16
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_CK_DELAY_MASK (0xf << 16)
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_HSDET_SEL_SHIFT 20
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_HSDET_SEL_MASK (0x3 << 20)
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_MANUAL_EN_SHIFT 24
> +#define MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_MANUAL_EN_MASK BIT(24)
> +#define MIPI_RX_ANA2C_CSI0A                                    0x002C
> +#define MIPI_RX_ANA2C_CSI0A_RG_CSI0A_CPHY_T0_CDR_INIT_CODE_SHIFT 0
> +#define MIPI_RX_ANA2C_CSI0A_RG_CSI0A_CPHY_T0_CDR_INIT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA2C_CSI0A_RG_CSI0A_CPHY_T0_CDR_EARLY_CODE_SHIFT 8
> +#define MIPI_RX_ANA2C_CSI0A_RG_CSI0A_CPHY_T0_CDR_EARLY_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA2C_CSI0A_RG_CSI0A_CPHY_T0_CDR_LATE_CODE_SHIFT 16
> +#define MIPI_RX_ANA2C_CSI0A_RG_CSI0A_CPHY_T0_CDR_LATE_CODE_MASK (0x1f << 16)
> +#define MIPI_RX_ANA34_CSI0A                                    0x0034
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_DIRECT_EN_SHIFT 0
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_DIRECT_EN_MASK BIT(0)
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_AUTOLOAD_EN_SHIFT 1
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_AUTOLOAD_EN_MASK BIT(1)
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_LPF_CTRL_SHIFT 2
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_LPF_CTRL_MASK (0x3 << 2)
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_AB_WIDTH_SHIFT 4
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_AB_WIDTH_MASK (0xf << 4)
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_BC_WIDTH_SHIFT 8
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_BC_WIDTH_MASK (0xf << 8)
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_CA_WIDTH_SHIFT 12
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_CA_WIDTH_MASK (0xf << 12)
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_CK_DELAY_SHIFT 16
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_CK_DELAY_MASK (0xf << 16)
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_HSDET_SEL_SHIFT 20
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_HSDET_SEL_MASK (0x3 << 20)
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_MANUAL_EN_SHIFT 24
> +#define MIPI_RX_ANA34_CSI0A_RG_CSI0A_CPHY_T1_CDR_MANUAL_EN_MASK BIT(24)
> +#define MIPI_RX_ANA38_CSI0A                                    0x0038
> +#define MIPI_RX_ANA38_CSI0A_RG_CSI0A_CPHY_T1_CDR_INIT_CODE_SHIFT 0
> +#define MIPI_RX_ANA38_CSI0A_RG_CSI0A_CPHY_T1_CDR_INIT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA38_CSI0A_RG_CSI0A_CPHY_T1_CDR_EARLY_CODE_SHIFT 8
> +#define MIPI_RX_ANA38_CSI0A_RG_CSI0A_CPHY_T1_CDR_EARLY_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA38_CSI0A_RG_CSI0A_CPHY_T1_CDR_LATE_CODE_SHIFT 16
> +#define MIPI_RX_ANA38_CSI0A_RG_CSI0A_CPHY_T1_CDR_LATE_CODE_MASK (0x1f << 16)
> +#define MIPI_RX_ANA40_CSI0A                                    0x0040
> +#define MIPI_RX_ANA40_CSI0A_RG_CSI0A_CPHY_FMCK_SEL_SHIFT 0
> +#define MIPI_RX_ANA40_CSI0A_RG_CSI0A_CPHY_FMCK_SEL_MASK (0x3 << 0)
> +#define MIPI_RX_ANA40_CSI0A_RG_CSI0A_ASYNC_OPTION_SHIFT 4
> +#define MIPI_RX_ANA40_CSI0A_RG_CSI0A_ASYNC_OPTION_MASK (0xf << 4)
> +#define MIPI_RX_ANA40_CSI0A_RG_CSI0A_CPHY_SPARE_SHIFT 16
> +#define MIPI_RX_ANA40_CSI0A_RG_CSI0A_CPHY_SPARE_MASK (0xffff << 16)
> +#define MIPI_RX_ANA48_CSI0A                                    0x0048
> +#define MIPI_RX_ANA48_CSI0A_RGS_CSI0A_CDPHY_L0_T0AB_OS_CAL_CPLT_SHIFT 0
> +#define MIPI_RX_ANA48_CSI0A_RGS_CSI0A_CDPHY_L0_T0AB_OS_CAL_CPLT_MASK BIT(0)
> +#define MIPI_RX_ANA48_CSI0A_RGS_CSI0A_CPHY_T0CA_OS_CAL_CPLT_SHIFT 1
> +#define MIPI_RX_ANA48_CSI0A_RGS_CSI0A_CPHY_T0CA_OS_CAL_CPLT_MASK BIT(1)
> +#define MIPI_RX_ANA48_CSI0A_RGS_CSI0A_CPHY_T0BC_OS_CAL_CPLT_SHIFT 2
> +#define MIPI_RX_ANA48_CSI0A_RGS_CSI0A_CPHY_T0BC_OS_CAL_CPLT_MASK BIT(2)
> +#define MIPI_RX_ANA48_CSI0A_RGS_CSI0A_CDPHY_L1_T1AB_OS_CAL_CPLT_SHIFT 3
> +#define MIPI_RX_ANA48_CSI0A_RGS_CSI0A_CDPHY_L1_T1AB_OS_CAL_CPLT_MASK BIT(3)
> +#define MIPI_RX_ANA48_CSI0A_RGS_CSI0A_CPHY_T1CA_OS_CAL_CPLT_SHIFT 4
> +#define MIPI_RX_ANA48_CSI0A_RGS_CSI0A_CPHY_T1CA_OS_CAL_CPLT_MASK BIT(4)
> +#define MIPI_RX_ANA48_CSI0A_RGS_CSI0A_CDPHY_L2_T1BC_OS_CAL_CPLT_SHIFT 5
> +#define MIPI_RX_ANA48_CSI0A_RGS_CSI0A_CDPHY_L2_T1BC_OS_CAL_CPLT_MASK BIT(5)
> +#define MIPI_RX_ANA48_CSI0A_RGS_CSI0A_OS_CAL_CODE_SHIFT 8
> +#define MIPI_RX_ANA48_CSI0A_RGS_CSI0A_OS_CAL_CODE_MASK (0xff << 8)
> +#define MIPI_RX_WRAPPER80_CSI0A                                0x0080
> +#define MIPI_RX_WRAPPER80_CSI0A_CSR_CSI_CLK_MON_SHIFT 0
> +#define MIPI_RX_WRAPPER80_CSI0A_CSR_CSI_CLK_MON_MASK BIT(0)
> +#define MIPI_RX_WRAPPER80_CSI0A_CSR_CSI_CLK_EN_SHIFT 1
> +#define MIPI_RX_WRAPPER80_CSI0A_CSR_CSI_CLK_EN_MASK BIT(1)
> +#define MIPI_RX_WRAPPER80_CSI0A_CSR_CSI_MON_MUX_SHIFT 8
> +#define MIPI_RX_WRAPPER80_CSI0A_CSR_CSI_MON_MUX_MASK (0xff << 8)
> +#define MIPI_RX_WRAPPER80_CSI0A_CSR_CSI_RST_MODE_SHIFT 16
> +#define MIPI_RX_WRAPPER80_CSI0A_CSR_CSI_RST_MODE_MASK (0x3 << 16)
> +#define MIPI_RX_WRAPPER80_CSI0A_CSR_SW_RST_SHIFT 24
> +#define MIPI_RX_WRAPPER80_CSI0A_CSR_SW_RST_MASK (0xf << 24)
> +#define MIPI_RX_WRAPPER84_CSI0A                                0x0084
> +#define MIPI_RX_WRAPPER84_CSI0A_CSI_DEBUG_OUT_SHIFT 0
> +#define MIPI_RX_WRAPPER84_CSI0A_CSI_DEBUG_OUT_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER88_CSI0A                                0x0088
> +#define MIPI_RX_WRAPPER88_CSI0A_CSR_SW_MODE_0_SHIFT 0
> +#define MIPI_RX_WRAPPER88_CSI0A_CSR_SW_MODE_0_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER8C_CSI0A                                0x008C
> +#define MIPI_RX_WRAPPER8C_CSI0A_CSR_SW_MODE_1_SHIFT 0
> +#define MIPI_RX_WRAPPER8C_CSI0A_CSR_SW_MODE_1_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER90_CSI0A                                0x0090
> +#define MIPI_RX_WRAPPER90_CSI0A_CSR_SW_MODE_2_SHIFT 0
> +#define MIPI_RX_WRAPPER90_CSI0A_CSR_SW_MODE_2_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER94_CSI0A                                0x0094
> +#define MIPI_RX_WRAPPER94_CSI0A_CSR_SW_VALUE_0_SHIFT 0
> +#define MIPI_RX_WRAPPER94_CSI0A_CSR_SW_VALUE_0_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER98_CSI0A                                0x0098
> +#define MIPI_RX_WRAPPER98_CSI0A_CSR_SW_VALUE_1_SHIFT 0
> +#define MIPI_RX_WRAPPER98_CSI0A_CSR_SW_VALUE_1_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER9C_CSI0A                                0x009C
> +#define MIPI_RX_WRAPPER9C_CSI0A_CSR_SW_VALUE_2_SHIFT 0
> +#define MIPI_RX_WRAPPER9C_CSI0A_CSR_SW_VALUE_2_MASK (0xffffffff << 0)
> +#define MIPI_RX_ANAA4_CSI0A                                    0x00A4
> +#define MIPI_RX_ANAA4_CSI0A_RG_CSI0A_CDPHY_L0_T0_SYNC_INIT_SEL_SHIFT 0
> +#define MIPI_RX_ANAA4_CSI0A_RG_CSI0A_CDPHY_L0_T0_SYNC_INIT_SEL_MASK BIT(0)
> +#define MIPI_RX_ANAA4_CSI0A_RG_CSI0A_CDPHY_L0_T0_FORCE_INIT_SHIFT 1
> +#define MIPI_RX_ANAA4_CSI0A_RG_CSI0A_CDPHY_L0_T0_FORCE_INIT_MASK BIT(1)
> +#define MIPI_RX_ANAA4_CSI0A_RG_CSI0A_DPHY_L1_SYNC_INIT_SEL_SHIFT 2
> +#define MIPI_RX_ANAA4_CSI0A_RG_CSI0A_DPHY_L1_SYNC_INIT_SEL_MASK BIT(2)
> +#define MIPI_RX_ANAA4_CSI0A_RG_CSI0A_DPHY_L1_FORCE_INIT_SHIFT 3
> +#define MIPI_RX_ANAA4_CSI0A_RG_CSI0A_DPHY_L1_FORCE_INIT_MASK BIT(3)
> +#define MIPI_RX_ANAA4_CSI0A_RG_CSI0A_CDPHY_L2_T1_SYNC_INIT_SEL_SHIFT 4
> +#define MIPI_RX_ANAA4_CSI0A_RG_CSI0A_CDPHY_L2_T1_SYNC_INIT_SEL_MASK BIT(4)
> +#define MIPI_RX_ANAA4_CSI0A_RG_CSI0A_CDPHY_L2_T1_FORCE_INIT_SHIFT 5
> +#define MIPI_RX_ANAA4_CSI0A_RG_CSI0A_CDPHY_L2_T1_FORCE_INIT_MASK BIT(5)
> +#define MIPI_RX_ANAA8_CSI0A                                    0x00A8
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_CDPHY_L0_T0_BYTECK_INVERT_SHIFT 0
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_CDPHY_L0_T0_BYTECK_INVERT_MASK BIT(0)
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_DPHY_L1_BYTECK_INVERT_SHIFT 1
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_DPHY_L1_BYTECK_INVERT_MASK BIT(1)
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_CDPHY_L2_T1_BYTECK_INVERT_SHIFT 2
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_CDPHY_L2_T1_BYTECK_INVERT_MASK BIT(2)
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_DPHY_HSDET_LEVEL_MODE_EN_SHIFT 3
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_DPHY_HSDET_LEVEL_MODE_EN_MASK BIT(3)
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_OS_CAL_SEL_SHIFT 4
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_OS_CAL_SEL_MASK (0x7 << 4)
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_DPHY_HSDET_DIG_BACK_EN_SHIFT 7
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_DPHY_HSDET_DIG_BACK_EN_MASK BIT(7)
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_CDPHY_DELAYCAL_CK_SEL_SHIFT 8
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_CDPHY_DELAYCAL_CK_SEL_MASK (0x7 << 8)
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_OS_CAL_DIV_SHIFT 11
> +#define MIPI_RX_ANAA8_CSI0A_RG_CSI0A_OS_CAL_DIV_MASK (0x3 << 11)
> +#define MIPI_RX_ANA00_CSI0B                                    0x1000
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_CPHY_EN_SHIFT 0
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_CPHY_EN_MASK BIT(0)
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_EQ_PROTECT_EN_SHIFT 1
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_EQ_PROTECT_EN_MASK BIT(1)
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_BG_LPF_EN_SHIFT 2
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_BG_LPF_EN_MASK BIT(2)
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_BG_CORE_EN_SHIFT 3
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_BG_CORE_EN_MASK BIT(3)
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_DPHY_L0_CKMODE_EN_SHIFT 5
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_DPHY_L0_CKMODE_EN_MASK BIT(5)
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_DPHY_L0_CKSEL_SHIFT 6
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_DPHY_L0_CKSEL_MASK BIT(6)
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_DPHY_L1_CKMODE_EN_SHIFT 8
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_DPHY_L1_CKMODE_EN_MASK BIT(8)
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_DPHY_L1_CKSEL_SHIFT 9
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_DPHY_L1_CKSEL_MASK BIT(9)
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_DPHY_L2_CKMODE_EN_SHIFT 11
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_DPHY_L2_CKMODE_EN_MASK BIT(11)
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_DPHY_L2_CKSEL_SHIFT 12
> +#define MIPI_RX_ANA00_CSI0B_RG_CSI0B_DPHY_L2_CKSEL_MASK BIT(12)
> +#define MIPI_RX_ANA04_CSI0B                                    0x1004
> +#define MIPI_RX_ANA04_CSI0B_RG_CSI0B_BG_LPRX_VTH_SEL_SHIFT 0
> +#define MIPI_RX_ANA04_CSI0B_RG_CSI0B_BG_LPRX_VTH_SEL_MASK (0x7 << 0)
> +#define MIPI_RX_ANA04_CSI0B_RG_CSI0B_BG_LPRX_VTL_SEL_SHIFT 4
> +#define MIPI_RX_ANA04_CSI0B_RG_CSI0B_BG_LPRX_VTL_SEL_MASK (0x7 << 4)
> +#define MIPI_RX_ANA04_CSI0B_RG_CSI0B_BG_HSDET_VTH_SEL_SHIFT 8
> +#define MIPI_RX_ANA04_CSI0B_RG_CSI0B_BG_HSDET_VTH_SEL_MASK (0x7 << 8)
> +#define MIPI_RX_ANA04_CSI0B_RG_CSI0B_BG_HSDET_VTL_SEL_SHIFT 12
> +#define MIPI_RX_ANA04_CSI0B_RG_CSI0B_BG_HSDET_VTL_SEL_MASK (0x7 << 12)
> +#define MIPI_RX_ANA04_CSI0B_RG_CSI0B_BG_VREF_SEL_SHIFT 16
> +#define MIPI_RX_ANA04_CSI0B_RG_CSI0B_BG_VREF_SEL_MASK (0xf << 16)
> +#define MIPI_RX_ANA04_CSI0B_RG_CSI0B_BG_MON_VREF_SEL_SHIFT 24
> +#define MIPI_RX_ANA04_CSI0B_RG_CSI0B_BG_MON_VREF_SEL_MASK (0xf << 24)
> +#define MIPI_RX_ANA04_CSI0B_RG_CSI0B_FORCE_HSRT_EN_SHIFT 28
> +#define MIPI_RX_ANA04_CSI0B_RG_CSI0B_FORCE_HSRT_EN_MASK BIT(28)
> +#define MIPI_RX_ANA08_CSI0B                                    0x1008
> +#define MIPI_RX_ANA08_CSI0B_RG_CSI0B_L0P_T0A_HSRT_CODE_SHIFT 0
> +#define MIPI_RX_ANA08_CSI0B_RG_CSI0B_L0P_T0A_HSRT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA08_CSI0B_RG_CSI0B_L0N_T0B_HSRT_CODE_SHIFT 8
> +#define MIPI_RX_ANA08_CSI0B_RG_CSI0B_L0N_T0B_HSRT_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA08_CSI0B_RG_CSI0B_L1P_T0C_HSRT_CODE_SHIFT 16
> +#define MIPI_RX_ANA08_CSI0B_RG_CSI0B_L1P_T0C_HSRT_CODE_MASK (0x1f << 16)
> +#define MIPI_RX_ANA08_CSI0B_RG_CSI0B_L1N_T1A_HSRT_CODE_SHIFT 24
> +#define MIPI_RX_ANA08_CSI0B_RG_CSI0B_L1N_T1A_HSRT_CODE_MASK (0x1f << 24)
> +#define MIPI_RX_ANA0C_CSI0B                                    0x100C
> +#define MIPI_RX_ANA0C_CSI0B_RG_CSI0B_L2P_T1B_HSRT_CODE_SHIFT 0
> +#define MIPI_RX_ANA0C_CSI0B_RG_CSI0B_L2P_T1B_HSRT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA0C_CSI0B_RG_CSI0B_L2N_T1C_HSRT_CODE_SHIFT 8
> +#define MIPI_RX_ANA0C_CSI0B_RG_CSI0B_L2N_T1C_HSRT_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA10_CSI0B                                    0x1010
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L0_DELAYCAL_EN_SHIFT 0
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L0_DELAYCAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L0_DELAYCAL_RSTB_SHIFT 1
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L0_DELAYCAL_RSTB_MASK BIT(1)
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L0_VREF_SEL_SHIFT 2
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L0_VREF_SEL_MASK (0x3f << 2)
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L1_DELAYCAL_EN_SHIFT 8
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L1_DELAYCAL_EN_MASK BIT(8)
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L1_DELAYCAL_RSTB_SHIFT 9
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L1_DELAYCAL_RSTB_MASK BIT(9)
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L1_VREF_SEL_SHIFT 10
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L1_VREF_SEL_MASK (0x3f << 10)
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L2_DELAYCAL_EN_SHIFT 16
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L2_DELAYCAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L2_DELAYCAL_RSTB_SHIFT 17
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L2_DELAYCAL_RSTB_MASK BIT(17)
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L2_VREF_SEL_SHIFT 18
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_DPHY_L2_VREF_SEL_MASK (0x3f << 18)
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_CPHY_T0_CDR_DELAYCAL_EN_SHIFT 24
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_CPHY_T0_CDR_DELAYCAL_EN_MASK BIT(24)
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_CPHY_T0_CDR_DELAYCAL_RSTB_SHIFT 25
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_CPHY_T0_CDR_DELAYCAL_RSTB_MASK BIT(25)
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_CPHY_T0_VREF_SEL_SHIFT 26
> +#define MIPI_RX_ANA10_CSI0B_RG_CSI0B_CPHY_T0_VREF_SEL_MASK (0x3f << 26)
> +#define MIPI_RX_ANA14_CSI0B                                    0x1014
> +#define MIPI_RX_ANA14_CSI0B_RG_CSI0B_CPHY_T1_CDR_DELAYCAL_EN_SHIFT 0
> +#define MIPI_RX_ANA14_CSI0B_RG_CSI0B_CPHY_T1_CDR_DELAYCAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA14_CSI0B_RG_CSI0B_CPHY_T1_CDR_DELAYCAL_RSTB_SHIFT 1
> +#define MIPI_RX_ANA14_CSI0B_RG_CSI0B_CPHY_T1_CDR_DELAYCAL_RSTB_MASK BIT(1)
> +#define MIPI_RX_ANA14_CSI0B_RG_CSI0B_CPHY_T1_VREF_SEL_SHIFT 2
> +#define MIPI_RX_ANA14_CSI0B_RG_CSI0B_CPHY_T1_VREF_SEL_MASK (0x3f << 2)
> +#define MIPI_RX_ANA18_CSI0B                                    0x1018
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_OS_CAL_EN_SHIFT 0
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_OS_CAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_MON_EN_SHIFT 1
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_MON_EN_MASK BIT(1)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_SCA_SHIFT 2
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_SCA_MASK BIT(2)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_SCB_SHIFT 3
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_SCB_MASK BIT(3)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_IS_SHIFT 4
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_IS_MASK (0x3 << 4)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_BW_SHIFT 6
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_BW_MASK (0x3 << 6)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_SRA_SHIFT 8
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_SRA_MASK (0xf << 8)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_SRB_SHIFT 12
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_L0_T0AB_EQ_SRB_MASK (0xf << 12)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_OS_CAL_EN_SHIFT 16
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_OS_CAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_MON_EN_SHIFT 17
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_MON_EN_MASK BIT(17)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_SCA_SHIFT 18
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_SCA_MASK BIT(18)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_SCB_SHIFT 19
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_SCB_MASK BIT(19)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_IS_SHIFT 20
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_IS_MASK (0x3 << 20)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_BW_SHIFT 22
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_BW_MASK (0x3 << 22)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_SRA_SHIFT 24
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_SRA_MASK (0xf << 24)
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_SRB_SHIFT 28
> +#define MIPI_RX_ANA18_CSI0B_RG_CSI0B_XX_T0CA_EQ_SRB_MASK (0xf << 28)
> +#define MIPI_RX_ANA1C_CSI0B                                    0x101C
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_OS_CAL_EN_SHIFT 0
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_OS_CAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_MON_EN_SHIFT 1
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_MON_EN_MASK BIT(1)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_SCA_SHIFT 2
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_SCA_MASK BIT(2)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_SCB_SHIFT 3
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_SCB_MASK BIT(3)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_IS_SHIFT 4
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_IS_MASK (0x3 << 4)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_BW_SHIFT 6
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_BW_MASK (0x3 << 6)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_SRA_SHIFT 8
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_SRA_MASK (0xf << 8)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_SRB_SHIFT 12
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_XX_T0BC_EQ_SRB_MASK (0xf << 12)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_OS_CAL_EN_SHIFT 16
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_OS_CAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_MON_EN_SHIFT 17
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_MON_EN_MASK BIT(17)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_SCA_SHIFT 18
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_SCA_MASK BIT(18)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_SCB_SHIFT 19
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_SCB_MASK BIT(19)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_IS_SHIFT 20
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_IS_MASK (0x3 << 20)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_BW_SHIFT 22
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_BW_MASK (0x3 << 22)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_SRA_SHIFT 24
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_SRA_MASK (0xf << 24)
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_SRB_SHIFT 28
> +#define MIPI_RX_ANA1C_CSI0B_RG_CSI0B_L1_T1AB_EQ_SRB_MASK (0xf << 28)
> +#define MIPI_RX_ANA20_CSI0B                                    0x1020
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_OS_CAL_EN_SHIFT 0
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_OS_CAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_MON_EN_SHIFT 1
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_MON_EN_MASK BIT(1)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_SCA_SHIFT 2
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_SCA_MASK BIT(2)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_SCB_SHIFT 3
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_SCB_MASK BIT(3)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_IS_SHIFT 4
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_IS_MASK (0x3 << 4)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_BW_SHIFT 6
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_BW_MASK (0x3 << 6)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_SRA_SHIFT 8
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_SRA_MASK (0xf << 8)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_SRB_SHIFT 12
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_XX_T1CA_EQ_SRB_MASK (0xf << 12)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_OS_CAL_EN_SHIFT 16
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_OS_CAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_MON_EN_SHIFT 17
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_MON_EN_MASK BIT(17)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_SCA_SHIFT 18
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_SCA_MASK BIT(18)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_SCB_SHIFT 19
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_SCB_MASK BIT(19)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_IS_SHIFT 20
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_IS_MASK (0x3 << 20)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_BW_SHIFT 22
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_BW_MASK (0x3 << 22)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_SRA_SHIFT 24
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_SRA_MASK (0xf << 24)
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_SRB_SHIFT 28
> +#define MIPI_RX_ANA20_CSI0B_RG_CSI0B_L2_T1BC_EQ_SRB_MASK (0xf << 28)
> +#define MIPI_RX_ANA24_CSI0B                                    0x1024
> +#define MIPI_RX_ANA24_CSI0B_RG_CSI0B_RESERVE_SHIFT 24
> +#define MIPI_RX_ANA24_CSI0B_RG_CSI0B_RESERVE_MASK (0xff << 24)
> +#define MIPI_RX_ANA28_CSI0B                                    0x1028
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_DIRECT_EN_SHIFT 0
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_DIRECT_EN_MASK BIT(0)
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_AUTOLOAD_EN_SHIFT 1
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_AUTOLOAD_EN_MASK BIT(1)
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_LPF_CTRL_SHIFT 2
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_LPF_CTRL_MASK (0x3 << 2)
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_AB_WIDTH_SHIFT 4
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_AB_WIDTH_MASK (0xf << 4)
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_BC_WIDTH_SHIFT 8
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_BC_WIDTH_MASK (0xf << 8)
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_CA_WIDTH_SHIFT 12
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_CA_WIDTH_MASK (0xf << 12)
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_CK_DELAY_SHIFT 16
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_CK_DELAY_MASK (0xf << 16)
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_HSDET_SEL_SHIFT 20
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_HSDET_SEL_MASK (0x3 << 20)
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_MANUAL_EN_SHIFT 24
> +#define MIPI_RX_ANA28_CSI0B_RG_CSI0B_CPHY_T0_CDR_MANUAL_EN_MASK BIT(24)
> +#define MIPI_RX_ANA2C_CSI0B                                    0x102C
> +#define MIPI_RX_ANA2C_CSI0B_RG_CSI0B_CPHY_T0_CDR_INIT_CODE_SHIFT 0
> +#define MIPI_RX_ANA2C_CSI0B_RG_CSI0B_CPHY_T0_CDR_INIT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA2C_CSI0B_RG_CSI0B_CPHY_T0_CDR_EARLY_CODE_SHIFT 8
> +#define MIPI_RX_ANA2C_CSI0B_RG_CSI0B_CPHY_T0_CDR_EARLY_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA2C_CSI0B_RG_CSI0B_CPHY_T0_CDR_LATE_CODE_SHIFT 16
> +#define MIPI_RX_ANA2C_CSI0B_RG_CSI0B_CPHY_T0_CDR_LATE_CODE_MASK (0x1f << 16)
> +#define MIPI_RX_ANA34_CSI0B                                    0x1034
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_DIRECT_EN_SHIFT 0
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_DIRECT_EN_MASK BIT(0)
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_AUTOLOAD_EN_SHIFT 1
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_AUTOLOAD_EN_MASK BIT(1)
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_LPF_CTRL_SHIFT 2
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_LPF_CTRL_MASK (0x3 << 2)
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_AB_WIDTH_SHIFT 4
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_AB_WIDTH_MASK (0xf << 4)
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_BC_WIDTH_SHIFT 8
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_BC_WIDTH_MASK (0xf << 8)
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_CA_WIDTH_SHIFT 12
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_CA_WIDTH_MASK (0xf << 12)
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_CK_DELAY_SHIFT 16
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_CK_DELAY_MASK (0xf << 16)
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_HSDET_SEL_SHIFT 20
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_HSDET_SEL_MASK (0x3 << 20)
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_MANUAL_EN_SHIFT 24
> +#define MIPI_RX_ANA34_CSI0B_RG_CSI0B_CPHY_T1_CDR_MANUAL_EN_MASK BIT(24)
> +#define MIPI_RX_ANA38_CSI0B                                    0x1038
> +#define MIPI_RX_ANA38_CSI0B_RG_CSI0B_CPHY_T1_CDR_INIT_CODE_SHIFT 0
> +#define MIPI_RX_ANA38_CSI0B_RG_CSI0B_CPHY_T1_CDR_INIT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA38_CSI0B_RG_CSI0B_CPHY_T1_CDR_EARLY_CODE_SHIFT 8
> +#define MIPI_RX_ANA38_CSI0B_RG_CSI0B_CPHY_T1_CDR_EARLY_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA38_CSI0B_RG_CSI0B_CPHY_T1_CDR_LATE_CODE_SHIFT 16
> +#define MIPI_RX_ANA38_CSI0B_RG_CSI0B_CPHY_T1_CDR_LATE_CODE_MASK (0x1f << 16)
> +#define MIPI_RX_ANA48_CSI0B                                    0x1048
> +#define MIPI_RX_ANA48_CSI0B_RGS_CSI0B_CDPHY_L0_T0AB_OS_CAL_CPLT_SHIFT 0
> +#define MIPI_RX_ANA48_CSI0B_RGS_CSI0B_CDPHY_L0_T0AB_OS_CAL_CPLT_MASK BIT(0)
> +#define MIPI_RX_ANA48_CSI0B_RGS_CSI0B_CPHY_T0CA_OS_CAL_CPLT_SHIFT 1
> +#define MIPI_RX_ANA48_CSI0B_RGS_CSI0B_CPHY_T0CA_OS_CAL_CPLT_MASK BIT(1)
> +#define MIPI_RX_ANA48_CSI0B_RGS_CSI0B_CPHY_T0BC_OS_CAL_CPLT_SHIFT 2
> +#define MIPI_RX_ANA48_CSI0B_RGS_CSI0B_CPHY_T0BC_OS_CAL_CPLT_MASK BIT(2)
> +#define MIPI_RX_ANA48_CSI0B_RGS_CSI0B_CDPHY_L1_T1AB_OS_CAL_CPLT_SHIFT 3
> +#define MIPI_RX_ANA48_CSI0B_RGS_CSI0B_CDPHY_L1_T1AB_OS_CAL_CPLT_MASK BIT(3)
> +#define MIPI_RX_ANA48_CSI0B_RGS_CSI0B_CPHY_T1CA_OS_CAL_CPLT_SHIFT 4
> +#define MIPI_RX_ANA48_CSI0B_RGS_CSI0B_CPHY_T1CA_OS_CAL_CPLT_MASK BIT(4)
> +#define MIPI_RX_ANA48_CSI0B_RGS_CSI0B_CDPHY_L2_T1BC_OS_CAL_CPLT_SHIFT 5
> +#define MIPI_RX_ANA48_CSI0B_RGS_CSI0B_CDPHY_L2_T1BC_OS_CAL_CPLT_MASK BIT(5)
> +#define MIPI_RX_ANA48_CSI0B_RGS_CSI0B_OS_CAL_CODE_SHIFT 8
> +#define MIPI_RX_ANA48_CSI0B_RGS_CSI0B_OS_CAL_CODE_MASK (0xff << 8)
> +#define MIPI_RX_WRAPPER80_CSI0B                                0x1080
> +#define MIPI_RX_WRAPPER80_CSI0B_CSR_CSI_CLK_MON_SHIFT 0
> +#define MIPI_RX_WRAPPER80_CSI0B_CSR_CSI_CLK_MON_MASK BIT(0)
> +#define MIPI_RX_WRAPPER80_CSI0B_CSR_CSI_CLK_EN_SHIFT 1
> +#define MIPI_RX_WRAPPER80_CSI0B_CSR_CSI_CLK_EN_MASK BIT(1)
> +#define MIPI_RX_WRAPPER80_CSI0B_CSR_CSI_MON_MUX_SHIFT 8
> +#define MIPI_RX_WRAPPER80_CSI0B_CSR_CSI_MON_MUX_MASK (0xff << 8)
> +#define MIPI_RX_WRAPPER80_CSI0B_CSR_CSI_RST_MODE_SHIFT 16
> +#define MIPI_RX_WRAPPER80_CSI0B_CSR_CSI_RST_MODE_MASK (0x3 << 16)
> +#define MIPI_RX_WRAPPER80_CSI0B_CSR_SW_RST_SHIFT 24
> +#define MIPI_RX_WRAPPER80_CSI0B_CSR_SW_RST_MASK (0xf << 24)
> +#define MIPI_RX_WRAPPER84_CSI0B                                0x1084
> +#define MIPI_RX_WRAPPER84_CSI0B_CSI_DEBUG_OUT_SHIFT 0
> +#define MIPI_RX_WRAPPER84_CSI0B_CSI_DEBUG_OUT_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER88_CSI0B                                0x1088
> +#define MIPI_RX_WRAPPER88_CSI0B_CSR_SW_MODE_0_SHIFT 0
> +#define MIPI_RX_WRAPPER88_CSI0B_CSR_SW_MODE_0_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER8C_CSI0B                                0x108C
> +#define MIPI_RX_WRAPPER8C_CSI0B_CSR_SW_MODE_1_SHIFT 0
> +#define MIPI_RX_WRAPPER8C_CSI0B_CSR_SW_MODE_1_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER90_CSI0B                                0x1090
> +#define MIPI_RX_WRAPPER90_CSI0B_CSR_SW_MODE_2_SHIFT 0
> +#define MIPI_RX_WRAPPER90_CSI0B_CSR_SW_MODE_2_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER94_CSI0B                                0x1094
> +#define MIPI_RX_WRAPPER94_CSI0B_CSR_SW_VALUE_0_SHIFT 0
> +#define MIPI_RX_WRAPPER94_CSI0B_CSR_SW_VALUE_0_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER98_CSI0B                                0x1098
> +#define MIPI_RX_WRAPPER98_CSI0B_CSR_SW_VALUE_1_SHIFT 0
> +#define MIPI_RX_WRAPPER98_CSI0B_CSR_SW_VALUE_1_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER9C_CSI0B                                0x109C
> +#define MIPI_RX_WRAPPER9C_CSI0B_CSR_SW_VALUE_2_SHIFT 0
> +#define MIPI_RX_WRAPPER9C_CSI0B_CSR_SW_VALUE_2_MASK (0xffffffff << 0)
> +#define MIPI_RX_ANAA4_CSI0B                                    0x10A4
> +#define MIPI_RX_ANAA4_CSI0B_RG_CSI0B_CDPHY_L0_T0_SYNC_INIT_SEL_SHIFT 0
> +#define MIPI_RX_ANAA4_CSI0B_RG_CSI0B_CDPHY_L0_T0_SYNC_INIT_SEL_MASK BIT(0)
> +#define MIPI_RX_ANAA4_CSI0B_RG_CSI0B_CDPHY_L0_T0_FORCE_INIT_SHIFT 1
> +#define MIPI_RX_ANAA4_CSI0B_RG_CSI0B_CDPHY_L0_T0_FORCE_INIT_MASK BIT(1)
> +#define MIPI_RX_ANAA4_CSI0B_RG_CSI0B_DPHY_L1_SYNC_INIT_SEL_SHIFT 2
> +#define MIPI_RX_ANAA4_CSI0B_RG_CSI0B_DPHY_L1_SYNC_INIT_SEL_MASK BIT(2)
> +#define MIPI_RX_ANAA4_CSI0B_RG_CSI0B_DPHY_L1_FORCE_INIT_SHIFT 3
> +#define MIPI_RX_ANAA4_CSI0B_RG_CSI0B_DPHY_L1_FORCE_INIT_MASK BIT(3)
> +#define MIPI_RX_ANAA4_CSI0B_RG_CSI0B_CDPHY_L2_T1_SYNC_INIT_SEL_SHIFT 4
> +#define MIPI_RX_ANAA4_CSI0B_RG_CSI0B_CDPHY_L2_T1_SYNC_INIT_SEL_MASK BIT(4)
> +#define MIPI_RX_ANAA4_CSI0B_RG_CSI0B_CDPHY_L2_T1_FORCE_INIT_SHIFT 5
> +#define MIPI_RX_ANAA4_CSI0B_RG_CSI0B_CDPHY_L2_T1_FORCE_INIT_MASK BIT(5)
> +#define MIPI_RX_ANAA8_CSI0B                                    0x10A8
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_CDPHY_L0_T0_BYTECK_INVERT_SHIFT 0
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_CDPHY_L0_T0_BYTECK_INVERT_MASK BIT(0)
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_DPHY_L1_BYTECK_INVERT_SHIFT 1
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_DPHY_L1_BYTECK_INVERT_MASK BIT(1)
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_CDPHY_L2_T1_BYTECK_INVERT_SHIFT 2
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_CDPHY_L2_T1_BYTECK_INVERT_MASK BIT(2)
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_DPHY_HSDET_LEVEL_MODE_EN_SHIFT 3
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_DPHY_HSDET_LEVEL_MODE_EN_MASK BIT(3)
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_OS_CAL_SEL_SHIFT 4
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_OS_CAL_SEL_MASK (0x7 << 4)
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_DPHY_HSDET_DIG_BACK_EN_SHIFT 7
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_DPHY_HSDET_DIG_BACK_EN_MASK BIT(7)
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_CDPHY_DELAYCAL_CK_SEL_SHIFT 8
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_CDPHY_DELAYCAL_CK_SEL_MASK (0x7 << 8)
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_OS_CAL_DIV_SHIFT 11
> +#define MIPI_RX_ANAA8_CSI0B_RG_CSI0B_OS_CAL_DIV_MASK (0x3 << 11)
> +#define MIPI_RX_ANA00_CSI1A                                    0x2000
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_EQ_PROTECT_EN_SHIFT 1
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_EQ_PROTECT_EN_MASK BIT(1)
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_BG_LPF_EN_SHIFT 2
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_BG_LPF_EN_MASK BIT(2)
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_BG_CORE_EN_SHIFT 3
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_BG_CORE_EN_MASK BIT(3)
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_DPHY_L0_CKMODE_EN_SHIFT 5
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_DPHY_L0_CKMODE_EN_MASK BIT(5)
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_DPHY_L0_CKSEL_SHIFT 6
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_DPHY_L0_CKSEL_MASK BIT(6)
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_DPHY_L1_CKMODE_EN_SHIFT 8
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_DPHY_L1_CKMODE_EN_MASK BIT(8)
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_DPHY_L1_CKSEL_SHIFT 9
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_DPHY_L1_CKSEL_MASK BIT(9)
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_DPHY_L2_CKMODE_EN_SHIFT 11
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_DPHY_L2_CKMODE_EN_MASK BIT(11)
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_DPHY_L2_CKSEL_SHIFT 12
> +#define MIPI_RX_ANA00_CSI1A_RG_CSI1A_DPHY_L2_CKSEL_MASK BIT(12)
> +#define MIPI_RX_ANA04_CSI1A                                    0x2004
> +#define MIPI_RX_ANA04_CSI1A_RG_CSI1A_BG_LPRX_VTH_SEL_SHIFT 0
> +#define MIPI_RX_ANA04_CSI1A_RG_CSI1A_BG_LPRX_VTH_SEL_MASK (0x7 << 0)
> +#define MIPI_RX_ANA04_CSI1A_RG_CSI1A_BG_LPRX_VTL_SEL_SHIFT 4
> +#define MIPI_RX_ANA04_CSI1A_RG_CSI1A_BG_LPRX_VTL_SEL_MASK (0x7 << 4)
> +#define MIPI_RX_ANA04_CSI1A_RG_CSI1A_BG_HSDET_VTH_SEL_SHIFT 8
> +#define MIPI_RX_ANA04_CSI1A_RG_CSI1A_BG_HSDET_VTH_SEL_MASK (0x7 << 8)
> +#define MIPI_RX_ANA04_CSI1A_RG_CSI1A_BG_HSDET_VTL_SEL_SHIFT 12
> +#define MIPI_RX_ANA04_CSI1A_RG_CSI1A_BG_HSDET_VTL_SEL_MASK (0x7 << 12)
> +#define MIPI_RX_ANA04_CSI1A_RG_CSI1A_BG_VREF_SEL_SHIFT 16
> +#define MIPI_RX_ANA04_CSI1A_RG_CSI1A_BG_VREF_SEL_MASK (0xf << 16)
> +#define MIPI_RX_ANA04_CSI1A_RG_CSI1A_BG_MON_VREF_SEL_SHIFT 24
> +#define MIPI_RX_ANA04_CSI1A_RG_CSI1A_BG_MON_VREF_SEL_MASK (0xf << 24)
> +#define MIPI_RX_ANA04_CSI1A_RG_CSI1A_FORCE_HSRT_EN_SHIFT 28
> +#define MIPI_RX_ANA04_CSI1A_RG_CSI1A_FORCE_HSRT_EN_MASK BIT(28)
> +#define MIPI_RX_ANA08_CSI1A                                    0x2008
> +#define MIPI_RX_ANA08_CSI1A_RG_CSI1A_L0P_HSRT_CODE_SHIFT 0
> +#define MIPI_RX_ANA08_CSI1A_RG_CSI1A_L0P_HSRT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA08_CSI1A_RG_CSI1A_L0N_HSRT_CODE_SHIFT 8
> +#define MIPI_RX_ANA08_CSI1A_RG_CSI1A_L0N_HSRT_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA08_CSI1A_RG_CSI1A_L1P_HSRT_CODE_SHIFT 16
> +#define MIPI_RX_ANA08_CSI1A_RG_CSI1A_L1P_HSRT_CODE_MASK (0x1f << 16)
> +#define MIPI_RX_ANA08_CSI1A_RG_CSI1A_L1N_HSRT_CODE_SHIFT 24
> +#define MIPI_RX_ANA08_CSI1A_RG_CSI1A_L1N_HSRT_CODE_MASK (0x1f << 24)
> +#define MIPI_RX_ANA0C_CSI1A                                    0x200C
> +#define MIPI_RX_ANA0C_CSI1A_RG_CSI1A_L2P_HSRT_CODE_SHIFT 0
> +#define MIPI_RX_ANA0C_CSI1A_RG_CSI1A_L2P_HSRT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA0C_CSI1A_RG_CSI1A_L2N_HSRT_CODE_SHIFT 8
> +#define MIPI_RX_ANA0C_CSI1A_RG_CSI1A_L2N_HSRT_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA10_CSI1A                                    0x2010
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L0_DELAYCAL_EN_SHIFT 0
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L0_DELAYCAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L0_DELAYCAL_RSTB_SHIFT 1
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L0_DELAYCAL_RSTB_MASK BIT(1)
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L0_VREF_SEL_SHIFT 2
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L0_VREF_SEL_MASK (0x3f << 2)
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L1_DELAYCAL_EN_SHIFT 8
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L1_DELAYCAL_EN_MASK BIT(8)
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L1_DELAYCAL_RSTB_SHIFT 9
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L1_DELAYCAL_RSTB_MASK BIT(9)
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L1_VREF_SEL_SHIFT 10
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L1_VREF_SEL_MASK (0x3f << 10)
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L2_DELAYCAL_EN_SHIFT 16
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L2_DELAYCAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L2_DELAYCAL_RSTB_SHIFT 17
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L2_DELAYCAL_RSTB_MASK BIT(17)
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L2_VREF_SEL_SHIFT 18
> +#define MIPI_RX_ANA10_CSI1A_RG_CSI1A_DPHY_L2_VREF_SEL_MASK (0x3f << 18)
> +#define MIPI_RX_ANA18_CSI1A                                    0x2018
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_OS_CAL_EN_SHIFT 0
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_OS_CAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_MON_EN_SHIFT 1
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_MON_EN_MASK BIT(1)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_SCA_SHIFT 2
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_SCA_MASK BIT(2)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_SCB_SHIFT 3
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_SCB_MASK BIT(3)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_IS_SHIFT 4
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_IS_MASK (0x3 << 4)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_BW_SHIFT 6
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_BW_MASK (0x3 << 6)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_SRA_SHIFT 8
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_SRA_MASK (0xf << 8)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_SRB_SHIFT 12
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L0_EQ_SRB_MASK (0xf << 12)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_OS_CAL_EN_SHIFT 16
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_OS_CAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_MON_EN_SHIFT 17
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_MON_EN_MASK BIT(17)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_SCA_SHIFT 18
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_SCA_MASK BIT(18)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_SCB_SHIFT 19
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_SCB_MASK BIT(19)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_IS_SHIFT 20
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_IS_MASK (0x3 << 20)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_BW_SHIFT 22
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_BW_MASK (0x3 << 22)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_SRA_SHIFT 24
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_SRA_MASK (0xf << 24)
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_SRB_SHIFT 28
> +#define MIPI_RX_ANA18_CSI1A_RG_CSI1A_L1_EQ_SRB_MASK (0xf << 28)
> +#define MIPI_RX_ANA1C_CSI1A                                    0x201C
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_OS_CAL_EN_SHIFT 0
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_OS_CAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_MON_EN_SHIFT 1
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_MON_EN_MASK BIT(1)
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_SCA_SHIFT 2
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_SCA_MASK BIT(2)
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_SCB_SHIFT 3
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_SCB_MASK BIT(3)
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_IS_SHIFT 4
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_IS_MASK (0x3 << 4)
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_BW_SHIFT 6
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_BW_MASK (0x3 << 6)
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_SRA_SHIFT 8
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_SRA_MASK (0xf << 8)
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_SRB_SHIFT 12
> +#define MIPI_RX_ANA1C_CSI1A_RG_CSI1A_L2_EQ_SRB_MASK (0xf << 12)
> +#define MIPI_RX_ANA24_CSI1A                                    0x2024
> +#define MIPI_RX_ANA24_CSI1A_RG_CSI1A_RESERVE_SHIFT 24
> +#define MIPI_RX_ANA24_CSI1A_RG_CSI1A_RESERVE_MASK (0xff << 24)
> +#define MIPI_RX_ANA48_CSI1A                                    0x2048
> +#define MIPI_RX_ANA48_CSI1A_RGS_CSI1A_DPHY_L0_OS_CAL_CPLT_SHIFT 3
> +#define MIPI_RX_ANA48_CSI1A_RGS_CSI1A_DPHY_L0_OS_CAL_CPLT_MASK BIT(3)
> +#define MIPI_RX_ANA48_CSI1A_RGS_CSI1A_DPHY_L1_OS_CAL_CPLT_SHIFT 4
> +#define MIPI_RX_ANA48_CSI1A_RGS_CSI1A_DPHY_L1_OS_CAL_CPLT_MASK BIT(4)
> +#define MIPI_RX_ANA48_CSI1A_RGS_CSI1A_DPHY_L2_OS_CAL_CPLT_SHIFT 5
> +#define MIPI_RX_ANA48_CSI1A_RGS_CSI1A_DPHY_L2_OS_CAL_CPLT_MASK BIT(5)
> +#define MIPI_RX_ANA48_CSI1A_RGS_CSI1A_OS_CAL_CODE_SHIFT 8
> +#define MIPI_RX_ANA48_CSI1A_RGS_CSI1A_OS_CAL_CODE_MASK (0xff << 8)
> +#define MIPI_RX_WRAPPER80_CSI1A                                0x2080
> +#define MIPI_RX_WRAPPER80_CSI1A_CSR_CSI_CLK_MON_SHIFT 0
> +#define MIPI_RX_WRAPPER80_CSI1A_CSR_CSI_CLK_MON_MASK BIT(0)
> +#define MIPI_RX_WRAPPER80_CSI1A_CSR_CSI_MON_MUX_SHIFT 8
> +#define MIPI_RX_WRAPPER80_CSI1A_CSR_CSI_MON_MUX_MASK (0xff << 8)
> +#define MIPI_RX_WRAPPER80_CSI1A_CSR_CSI_RST_MODE_SHIFT 16
> +#define MIPI_RX_WRAPPER80_CSI1A_CSR_CSI_RST_MODE_MASK (0x3 << 16)
> +#define MIPI_RX_WRAPPER80_CSI1A_CSR_SW_RST_SHIFT 24
> +#define MIPI_RX_WRAPPER80_CSI1A_CSR_SW_RST_MASK (0xf << 24)
> +#define MIPI_RX_WRAPPER84_CSI1A                                0x2084
> +#define MIPI_RX_WRAPPER84_CSI1A_CSI_DEBUG_OUT_SHIFT 0
> +#define MIPI_RX_WRAPPER84_CSI1A_CSI_DEBUG_OUT_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER88_CSI1A                                0x2088
> +#define MIPI_RX_WRAPPER88_CSI1A_CSR_SW_MODE_0_SHIFT 0
> +#define MIPI_RX_WRAPPER88_CSI1A_CSR_SW_MODE_0_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER8C_CSI1A                                0x208C
> +#define MIPI_RX_WRAPPER8C_CSI1A_CSR_SW_MODE_1_SHIFT 0
> +#define MIPI_RX_WRAPPER8C_CSI1A_CSR_SW_MODE_1_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER90_CSI1A                                0x2090
> +#define MIPI_RX_WRAPPER90_CSI1A_CSR_SW_MODE_2_SHIFT 0
> +#define MIPI_RX_WRAPPER90_CSI1A_CSR_SW_MODE_2_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER94_CSI1A                                0x2094
> +#define MIPI_RX_WRAPPER94_CSI1A_CSR_SW_VALUE_0_SHIFT 0
> +#define MIPI_RX_WRAPPER94_CSI1A_CSR_SW_VALUE_0_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER98_CSI1A                                0x2098
> +#define MIPI_RX_WRAPPER98_CSI1A_CSR_SW_VALUE_1_SHIFT 0
> +#define MIPI_RX_WRAPPER98_CSI1A_CSR_SW_VALUE_1_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER9C_CSI1A                                0x209C
> +#define MIPI_RX_WRAPPER9C_CSI1A_CSR_SW_VALUE_2_SHIFT 0
> +#define MIPI_RX_WRAPPER9C_CSI1A_CSR_SW_VALUE_2_MASK (0xffffffff << 0)
> +#define MIPI_RX_ANAA4_CSI1A                                    0x20A4
> +#define MIPI_RX_ANAA4_CSI1A_RG_CSI1A_DPHY_L0_SYNC_INIT_SEL_SHIFT 0
> +#define MIPI_RX_ANAA4_CSI1A_RG_CSI1A_DPHY_L0_SYNC_INIT_SEL_MASK BIT(0)
> +#define MIPI_RX_ANAA4_CSI1A_RG_CSI1A_DPHY_L0_FORCE_INIT_SHIFT 1
> +#define MIPI_RX_ANAA4_CSI1A_RG_CSI1A_DPHY_L0_FORCE_INIT_MASK BIT(1)
> +#define MIPI_RX_ANAA4_CSI1A_RG_CSI1A_DPHY_L1_SYNC_INIT_SEL_SHIFT 2
> +#define MIPI_RX_ANAA4_CSI1A_RG_CSI1A_DPHY_L1_SYNC_INIT_SEL_MASK BIT(2)
> +#define MIPI_RX_ANAA4_CSI1A_RG_CSI1A_DPHY_L1_FORCE_INIT_SHIFT 3
> +#define MIPI_RX_ANAA4_CSI1A_RG_CSI1A_DPHY_L1_FORCE_INIT_MASK BIT(3)
> +#define MIPI_RX_ANAA4_CSI1A_RG_CSI1A_DPHY_L2_SYNC_INIT_SEL_SHIFT 4
> +#define MIPI_RX_ANAA4_CSI1A_RG_CSI1A_DPHY_L2_SYNC_INIT_SEL_MASK BIT(4)
> +#define MIPI_RX_ANAA4_CSI1A_RG_CSI1A_DPHY_L2_FORCE_INIT_SHIFT 5
> +#define MIPI_RX_ANAA4_CSI1A_RG_CSI1A_DPHY_L2_FORCE_INIT_MASK BIT(5)
> +#define MIPI_RX_ANAA8_CSI1A                                    0x20A8
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_DPHY_L0_BYTECK_INVERT_SHIFT 0
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_DPHY_L0_BYTECK_INVERT_MASK BIT(0)
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_DPHY_L1_BYTECK_INVERT_SHIFT 1
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_DPHY_L1_BYTECK_INVERT_MASK BIT(1)
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_DPHY_L2_BYTECK_INVERT_SHIFT 2
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_DPHY_L2_BYTECK_INVERT_MASK BIT(2)
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_DPHY_HSDET_LEVEL_MODE_EN_SHIFT 3
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_DPHY_HSDET_LEVEL_MODE_EN_MASK BIT(3)
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_OS_CAL_SEL_SHIFT 4
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_OS_CAL_SEL_MASK (0x7 << 4)
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_DPHY_HSDET_DIG_BACK_EN_SHIFT 7
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_DPHY_HSDET_DIG_BACK_EN_MASK BIT(7)
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_DPHY_DELAYCAL_CK_SEL_SHIFT 8
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_DPHY_DELAYCAL_CK_SEL_MASK (0x7 << 8)
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_OS_CAL_DIV_SHIFT 11
> +#define MIPI_RX_ANAA8_CSI1A_RG_CSI1A_OS_CAL_DIV_MASK (0x3 << 11)
> +#define MIPI_RX_ANA00_CSI1B                                    0x3000
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_EQ_PROTECT_EN_SHIFT 1
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_EQ_PROTECT_EN_MASK BIT(1)
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_BG_LPF_EN_SHIFT 2
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_BG_LPF_EN_MASK BIT(2)
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_BG_CORE_EN_SHIFT 3
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_BG_CORE_EN_MASK BIT(3)
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_DPHY_L0_CKMODE_EN_SHIFT 5
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_DPHY_L0_CKMODE_EN_MASK BIT(5)
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_DPHY_L0_CKSEL_SHIFT 6
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_DPHY_L0_CKSEL_MASK BIT(6)
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_DPHY_L1_CKMODE_EN_SHIFT 8
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_DPHY_L1_CKMODE_EN_MASK BIT(8)
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_DPHY_L1_CKSEL_SHIFT 9
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_DPHY_L1_CKSEL_MASK BIT(9)
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_DPHY_L2_CKMODE_EN_SHIFT 11
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_DPHY_L2_CKMODE_EN_MASK BIT(11)
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_DPHY_L2_CKSEL_SHIFT 12
> +#define MIPI_RX_ANA00_CSI1B_RG_CSI1B_DPHY_L2_CKSEL_MASK BIT(12)
> +#define MIPI_RX_ANA04_CSI1B                                    0x3004
> +#define MIPI_RX_ANA04_CSI1B_RG_CSI1B_BG_LPRX_VTH_SEL_SHIFT 0
> +#define MIPI_RX_ANA04_CSI1B_RG_CSI1B_BG_LPRX_VTH_SEL_MASK (0x7 << 0)
> +#define MIPI_RX_ANA04_CSI1B_RG_CSI1B_BG_LPRX_VTL_SEL_SHIFT 4
> +#define MIPI_RX_ANA04_CSI1B_RG_CSI1B_BG_LPRX_VTL_SEL_MASK (0x7 << 4)
> +#define MIPI_RX_ANA04_CSI1B_RG_CSI1B_BG_HSDET_VTH_SEL_SHIFT 8
> +#define MIPI_RX_ANA04_CSI1B_RG_CSI1B_BG_HSDET_VTH_SEL_MASK (0x7 << 8)
> +#define MIPI_RX_ANA04_CSI1B_RG_CSI1B_BG_HSDET_VTL_SEL_SHIFT 12
> +#define MIPI_RX_ANA04_CSI1B_RG_CSI1B_BG_HSDET_VTL_SEL_MASK (0x7 << 12)
> +#define MIPI_RX_ANA04_CSI1B_RG_CSI1B_BG_VREF_SEL_SHIFT 16
> +#define MIPI_RX_ANA04_CSI1B_RG_CSI1B_BG_VREF_SEL_MASK (0xf << 16)
> +#define MIPI_RX_ANA04_CSI1B_RG_CSI1B_BG_MON_VREF_SEL_SHIFT 24
> +#define MIPI_RX_ANA04_CSI1B_RG_CSI1B_BG_MON_VREF_SEL_MASK (0xf << 24)
> +#define MIPI_RX_ANA04_CSI1B_RG_CSI1B_FORCE_HSRT_EN_SHIFT 28
> +#define MIPI_RX_ANA04_CSI1B_RG_CSI1B_FORCE_HSRT_EN_MASK BIT(28)
> +#define MIPI_RX_ANA08_CSI1B                                    0x3008
> +#define MIPI_RX_ANA08_CSI1B_RG_CSI1B_L0P_HSRT_CODE_SHIFT 0
> +#define MIPI_RX_ANA08_CSI1B_RG_CSI1B_L0P_HSRT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA08_CSI1B_RG_CSI1B_L0N_HSRT_CODE_SHIFT 8
> +#define MIPI_RX_ANA08_CSI1B_RG_CSI1B_L0N_HSRT_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA08_CSI1B_RG_CSI1B_L1P_HSRT_CODE_SHIFT 16
> +#define MIPI_RX_ANA08_CSI1B_RG_CSI1B_L1P_HSRT_CODE_MASK (0x1f << 16)
> +#define MIPI_RX_ANA08_CSI1B_RG_CSI1B_L1N_HSRT_CODE_SHIFT 24
> +#define MIPI_RX_ANA08_CSI1B_RG_CSI1B_L1N_HSRT_CODE_MASK (0x1f << 24)
> +#define MIPI_RX_ANA0C_CSI1B                                    0x300C
> +#define MIPI_RX_ANA0C_CSI1B_RG_CSI1B_L2P_HSRT_CODE_SHIFT 0
> +#define MIPI_RX_ANA0C_CSI1B_RG_CSI1B_L2P_HSRT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA0C_CSI1B_RG_CSI1B_L2N_HSRT_CODE_SHIFT 8
> +#define MIPI_RX_ANA0C_CSI1B_RG_CSI1B_L2N_HSRT_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA10_CSI1B                                    0x3010
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L0_DELAYCAL_EN_SHIFT 0
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L0_DELAYCAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L0_DELAYCAL_RSTB_SHIFT 1
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L0_DELAYCAL_RSTB_MASK BIT(1)
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L0_VREF_SEL_SHIFT 2
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L0_VREF_SEL_MASK (0x3f << 2)
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L1_DELAYCAL_EN_SHIFT 8
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L1_DELAYCAL_EN_MASK BIT(8)
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L1_DELAYCAL_RSTB_SHIFT 9
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L1_DELAYCAL_RSTB_MASK BIT(9)
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L1_VREF_SEL_SHIFT 10
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L1_VREF_SEL_MASK (0x3f << 10)
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L2_DELAYCAL_EN_SHIFT 16
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L2_DELAYCAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L2_DELAYCAL_RSTB_SHIFT 17
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L2_DELAYCAL_RSTB_MASK BIT(17)
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L2_VREF_SEL_SHIFT 18
> +#define MIPI_RX_ANA10_CSI1B_RG_CSI1B_DPHY_L2_VREF_SEL_MASK (0x3f << 18)
> +#define MIPI_RX_ANA18_CSI1B                                    0x3018
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_OS_CAL_EN_SHIFT 0
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_OS_CAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_MON_EN_SHIFT 1
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_MON_EN_MASK BIT(1)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_SCA_SHIFT 2
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_SCA_MASK BIT(2)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_SCB_SHIFT 3
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_SCB_MASK BIT(3)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_IS_SHIFT 4
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_IS_MASK (0x3 << 4)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_BW_SHIFT 6
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_BW_MASK (0x3 << 6)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_SRA_SHIFT 8
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_SRA_MASK (0xf << 8)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_SRB_SHIFT 12
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L0_EQ_SRB_MASK (0xf << 12)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_OS_CAL_EN_SHIFT 16
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_OS_CAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_MON_EN_SHIFT 17
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_MON_EN_MASK BIT(17)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_SCA_SHIFT 18
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_SCA_MASK BIT(18)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_SCB_SHIFT 19
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_SCB_MASK BIT(19)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_IS_SHIFT 20
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_IS_MASK (0x3 << 20)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_BW_SHIFT 22
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_BW_MASK (0x3 << 22)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_SRA_SHIFT 24
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_SRA_MASK (0xf << 24)
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_SRB_SHIFT 28
> +#define MIPI_RX_ANA18_CSI1B_RG_CSI1B_L1_EQ_SRB_MASK (0xf << 28)
> +#define MIPI_RX_ANA1C_CSI1B                                    0x301C
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_OS_CAL_EN_SHIFT 0
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_OS_CAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_MON_EN_SHIFT 1
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_MON_EN_MASK BIT(1)
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_SCA_SHIFT 2
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_SCA_MASK BIT(2)
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_SCB_SHIFT 3
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_SCB_MASK BIT(3)
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_IS_SHIFT 4
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_IS_MASK (0x3 << 4)
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_BW_SHIFT 6
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_BW_MASK (0x3 << 6)
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_SRA_SHIFT 8
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_SRA_MASK (0xf << 8)
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_SRB_SHIFT 12
> +#define MIPI_RX_ANA1C_CSI1B_RG_CSI1B_L2_EQ_SRB_MASK (0xf << 12)
> +#define MIPI_RX_ANA24_CSI1B                                    0x3024
> +#define MIPI_RX_ANA24_CSI1B_RG_CSI1B_RESERVE_SHIFT 24
> +#define MIPI_RX_ANA24_CSI1B_RG_CSI1B_RESERVE_MASK (0xff << 24)
> +#define MIPI_RX_ANA48_CSI1B                                    0x3048
> +#define MIPI_RX_ANA48_CSI1B_RGS_CSI1B_DPHY_L0_OS_CAL_CPLT_SHIFT 3
> +#define MIPI_RX_ANA48_CSI1B_RGS_CSI1B_DPHY_L0_OS_CAL_CPLT_MASK BIT(3)
> +#define MIPI_RX_ANA48_CSI1B_RGS_CSI1B_DPHY_L1_OS_CAL_CPLT_SHIFT 4
> +#define MIPI_RX_ANA48_CSI1B_RGS_CSI1B_DPHY_L1_OS_CAL_CPLT_MASK BIT(4)
> +#define MIPI_RX_ANA48_CSI1B_RGS_CSI1B_DPHY_L2_OS_CAL_CPLT_SHIFT 5
> +#define MIPI_RX_ANA48_CSI1B_RGS_CSI1B_DPHY_L2_OS_CAL_CPLT_MASK BIT(5)
> +#define MIPI_RX_ANA48_CSI1B_RGS_CSI1B_OS_CAL_CODE_SHIFT 8
> +#define MIPI_RX_ANA48_CSI1B_RGS_CSI1B_OS_CAL_CODE_MASK (0xff << 8)
> +#define MIPI_RX_WRAPPER80_CSI1B                                0x3080
> +#define MIPI_RX_WRAPPER80_CSI1B_CSR_CSI_CLK_MON_SHIFT 0
> +#define MIPI_RX_WRAPPER80_CSI1B_CSR_CSI_CLK_MON_MASK BIT(0)
> +#define MIPI_RX_WRAPPER80_CSI1B_CSR_CSI_MON_MUX_SHIFT 8
> +#define MIPI_RX_WRAPPER80_CSI1B_CSR_CSI_MON_MUX_MASK (0xff << 8)
> +#define MIPI_RX_WRAPPER80_CSI1B_CSR_CSI_RST_MODE_SHIFT 16
> +#define MIPI_RX_WRAPPER80_CSI1B_CSR_CSI_RST_MODE_MASK (0x3 << 16)
> +#define MIPI_RX_WRAPPER80_CSI1B_CSR_SW_RST_SHIFT 24
> +#define MIPI_RX_WRAPPER80_CSI1B_CSR_SW_RST_MASK (0xf << 24)
> +#define MIPI_RX_WRAPPER84_CSI1B                                0x3084
> +#define MIPI_RX_WRAPPER84_CSI1B_CSI_DEBUG_OUT_SHIFT 0
> +#define MIPI_RX_WRAPPER84_CSI1B_CSI_DEBUG_OUT_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER88_CSI1B                                0x3088
> +#define MIPI_RX_WRAPPER88_CSI1B_CSR_SW_MODE_0_SHIFT 0
> +#define MIPI_RX_WRAPPER88_CSI1B_CSR_SW_MODE_0_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER8C_CSI1B                                0x308C
> +#define MIPI_RX_WRAPPER8C_CSI1B_CSR_SW_MODE_1_SHIFT 0
> +#define MIPI_RX_WRAPPER8C_CSI1B_CSR_SW_MODE_1_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER90_CSI1B                                0x3090
> +#define MIPI_RX_WRAPPER90_CSI1B_CSR_SW_MODE_2_SHIFT 0
> +#define MIPI_RX_WRAPPER90_CSI1B_CSR_SW_MODE_2_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER94_CSI1B                                0x3094
> +#define MIPI_RX_WRAPPER94_CSI1B_CSR_SW_VALUE_0_SHIFT 0
> +#define MIPI_RX_WRAPPER94_CSI1B_CSR_SW_VALUE_0_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER98_CSI1B                                0x3098
> +#define MIPI_RX_WRAPPER98_CSI1B_CSR_SW_VALUE_1_SHIFT 0
> +#define MIPI_RX_WRAPPER98_CSI1B_CSR_SW_VALUE_1_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER9C_CSI1B                                0x309C
> +#define MIPI_RX_WRAPPER9C_CSI1B_CSR_SW_VALUE_2_SHIFT 0
> +#define MIPI_RX_WRAPPER9C_CSI1B_CSR_SW_VALUE_2_MASK (0xffffffff << 0)
> +#define MIPI_RX_ANAA4_CSI1B                                    0x30A4
> +#define MIPI_RX_ANAA4_CSI1B_RG_CSI1B_DPHY_L0_SYNC_INIT_SEL_SHIFT 0
> +#define MIPI_RX_ANAA4_CSI1B_RG_CSI1B_DPHY_L0_SYNC_INIT_SEL_MASK BIT(0)
> +#define MIPI_RX_ANAA4_CSI1B_RG_CSI1B_DPHY_L0_FORCE_INIT_SHIFT 1
> +#define MIPI_RX_ANAA4_CSI1B_RG_CSI1B_DPHY_L0_FORCE_INIT_MASK BIT(1)
> +#define MIPI_RX_ANAA4_CSI1B_RG_CSI1B_DPHY_L1_SYNC_INIT_SEL_SHIFT 2
> +#define MIPI_RX_ANAA4_CSI1B_RG_CSI1B_DPHY_L1_SYNC_INIT_SEL_MASK BIT(2)
> +#define MIPI_RX_ANAA4_CSI1B_RG_CSI1B_DPHY_L1_FORCE_INIT_SHIFT 3
> +#define MIPI_RX_ANAA4_CSI1B_RG_CSI1B_DPHY_L1_FORCE_INIT_MASK BIT(3)
> +#define MIPI_RX_ANAA4_CSI1B_RG_CSI1B_DPHY_L2_SYNC_INIT_SEL_SHIFT 4
> +#define MIPI_RX_ANAA4_CSI1B_RG_CSI1B_DPHY_L2_SYNC_INIT_SEL_MASK BIT(4)
> +#define MIPI_RX_ANAA4_CSI1B_RG_CSI1B_DPHY_L2_FORCE_INIT_SHIFT 5
> +#define MIPI_RX_ANAA4_CSI1B_RG_CSI1B_DPHY_L2_FORCE_INIT_MASK BIT(5)
> +#define MIPI_RX_ANAA8_CSI1B                                    0x30A8
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_DPHY_L0_BYTECK_INVERT_SHIFT 0
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_DPHY_L0_BYTECK_INVERT_MASK BIT(0)
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_DPHY_L1_BYTECK_INVERT_SHIFT 1
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_DPHY_L1_BYTECK_INVERT_MASK BIT(1)
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_DPHY_L2_BYTECK_INVERT_SHIFT 2
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_DPHY_L2_BYTECK_INVERT_MASK BIT(2)
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_DPHY_HSDET_LEVEL_MODE_EN_SHIFT 3
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_DPHY_HSDET_LEVEL_MODE_EN_MASK BIT(3)
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_OS_CAL_SEL_SHIFT 4
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_OS_CAL_SEL_MASK (0x7 << 4)
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_DPHY_HSDET_DIG_BACK_EN_SHIFT 7
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_DPHY_HSDET_DIG_BACK_EN_MASK BIT(7)
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_DPHY_DELAYCAL_CK_SEL_SHIFT 8
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_DPHY_DELAYCAL_CK_SEL_MASK (0x7 << 8)
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_OS_CAL_DIV_SHIFT 11
> +#define MIPI_RX_ANAA8_CSI1B_RG_CSI1B_OS_CAL_DIV_MASK (0x3 << 11)
> +#define MIPI_RX_ANA00_CSI2A                                    0x4000
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_EQ_PROTECT_EN_SHIFT 1
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_EQ_PROTECT_EN_MASK BIT(1)
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_BG_LPF_EN_SHIFT 2
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_BG_LPF_EN_MASK BIT(2)
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_BG_CORE_EN_SHIFT 3
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_BG_CORE_EN_MASK BIT(3)
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_DPHY_L0_CKMODE_EN_SHIFT 5
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_DPHY_L0_CKMODE_EN_MASK BIT(5)
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_DPHY_L0_CKSEL_SHIFT 6
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_DPHY_L0_CKSEL_MASK BIT(6)
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_DPHY_L1_CKMODE_EN_SHIFT 8
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_DPHY_L1_CKMODE_EN_MASK BIT(8)
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_DPHY_L1_CKSEL_SHIFT 9
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_DPHY_L1_CKSEL_MASK BIT(9)
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_DPHY_L2_CKMODE_EN_SHIFT 11
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_DPHY_L2_CKMODE_EN_MASK BIT(11)
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_DPHY_L2_CKSEL_SHIFT 12
> +#define MIPI_RX_ANA00_CSI2A_RG_CSI2A_DPHY_L2_CKSEL_MASK BIT(12)
> +#define MIPI_RX_ANA04_CSI2A                                    0x4004
> +#define MIPI_RX_ANA04_CSI2A_RG_CSI2A_BG_LPRX_VTH_SEL_SHIFT 0
> +#define MIPI_RX_ANA04_CSI2A_RG_CSI2A_BG_LPRX_VTH_SEL_MASK (0x7 << 0)
> +#define MIPI_RX_ANA04_CSI2A_RG_CSI2A_BG_LPRX_VTL_SEL_SHIFT 4
> +#define MIPI_RX_ANA04_CSI2A_RG_CSI2A_BG_LPRX_VTL_SEL_MASK (0x7 << 4)
> +#define MIPI_RX_ANA04_CSI2A_RG_CSI2A_BG_HSDET_VTH_SEL_SHIFT 8
> +#define MIPI_RX_ANA04_CSI2A_RG_CSI2A_BG_HSDET_VTH_SEL_MASK (0x7 << 8)
> +#define MIPI_RX_ANA04_CSI2A_RG_CSI2A_BG_HSDET_VTL_SEL_SHIFT 12
> +#define MIPI_RX_ANA04_CSI2A_RG_CSI2A_BG_HSDET_VTL_SEL_MASK (0x7 << 12)
> +#define MIPI_RX_ANA04_CSI2A_RG_CSI2A_BG_VREF_SEL_SHIFT 16
> +#define MIPI_RX_ANA04_CSI2A_RG_CSI2A_BG_VREF_SEL_MASK (0xf << 16)
> +#define MIPI_RX_ANA04_CSI2A_RG_CSI2A_BG_MON_VREF_SEL_SHIFT 24
> +#define MIPI_RX_ANA04_CSI2A_RG_CSI2A_BG_MON_VREF_SEL_MASK (0xf << 24)
> +#define MIPI_RX_ANA04_CSI2A_RG_CSI2A_FORCE_HSRT_EN_SHIFT 28
> +#define MIPI_RX_ANA04_CSI2A_RG_CSI2A_FORCE_HSRT_EN_MASK BIT(28)
> +#define MIPI_RX_ANA08_CSI2A                                    0x4008
> +#define MIPI_RX_ANA08_CSI2A_RG_CSI2A_L0P_HSRT_CODE_SHIFT 0
> +#define MIPI_RX_ANA08_CSI2A_RG_CSI2A_L0P_HSRT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA08_CSI2A_RG_CSI2A_L0N_HSRT_CODE_SHIFT 8
> +#define MIPI_RX_ANA08_CSI2A_RG_CSI2A_L0N_HSRT_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA08_CSI2A_RG_CSI2A_L1P_HSRT_CODE_SHIFT 16
> +#define MIPI_RX_ANA08_CSI2A_RG_CSI2A_L1P_HSRT_CODE_MASK (0x1f << 16)
> +#define MIPI_RX_ANA08_CSI2A_RG_CSI2A_L1N_HSRT_CODE_SHIFT 24
> +#define MIPI_RX_ANA08_CSI2A_RG_CSI2A_L1N_HSRT_CODE_MASK (0x1f << 24)
> +#define MIPI_RX_ANA0C_CSI2A                                    0x400C
> +#define MIPI_RX_ANA0C_CSI2A_RG_CSI2A_L2P_HSRT_CODE_SHIFT 0
> +#define MIPI_RX_ANA0C_CSI2A_RG_CSI2A_L2P_HSRT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA0C_CSI2A_RG_CSI2A_L2N_HSRT_CODE_SHIFT 8
> +#define MIPI_RX_ANA0C_CSI2A_RG_CSI2A_L2N_HSRT_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA10_CSI2A                                    0x4010
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L0_DELAYCAL_EN_SHIFT 0
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L0_DELAYCAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L0_DELAYCAL_RSTB_SHIFT 1
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L0_DELAYCAL_RSTB_MASK BIT(1)
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L0_VREF_SEL_SHIFT 2
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L0_VREF_SEL_MASK (0x3f << 2)
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L1_DELAYCAL_EN_SHIFT 8
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L1_DELAYCAL_EN_MASK BIT(8)
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L1_DELAYCAL_RSTB_SHIFT 9
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L1_DELAYCAL_RSTB_MASK BIT(9)
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L1_VREF_SEL_SHIFT 10
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L1_VREF_SEL_MASK (0x3f << 10)
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L2_DELAYCAL_EN_SHIFT 16
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L2_DELAYCAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L2_DELAYCAL_RSTB_SHIFT 17
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L2_DELAYCAL_RSTB_MASK BIT(17)
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L2_VREF_SEL_SHIFT 18
> +#define MIPI_RX_ANA10_CSI2A_RG_CSI2A_DPHY_L2_VREF_SEL_MASK (0x3f << 18)
> +#define MIPI_RX_ANA18_CSI2A                                    0x4018
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_OS_CAL_EN_SHIFT 0
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_OS_CAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_MON_EN_SHIFT 1
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_MON_EN_MASK BIT(1)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_SCA_SHIFT 2
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_SCA_MASK BIT(2)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_SCB_SHIFT 3
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_SCB_MASK BIT(3)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_IS_SHIFT 4
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_IS_MASK (0x3 << 4)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_BW_SHIFT 6
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_BW_MASK (0x3 << 6)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_SRA_SHIFT 8
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_SRA_MASK (0xf << 8)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_SRB_SHIFT 12
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L0_EQ_SRB_MASK (0xf << 12)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_OS_CAL_EN_SHIFT 16
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_OS_CAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_MON_EN_SHIFT 17
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_MON_EN_MASK BIT(17)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_SCA_SHIFT 18
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_SCA_MASK BIT(18)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_SCB_SHIFT 19
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_SCB_MASK BIT(19)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_IS_SHIFT 20
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_IS_MASK (0x3 << 20)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_BW_SHIFT 22
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_BW_MASK (0x3 << 22)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_SRA_SHIFT 24
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_SRA_MASK (0xf << 24)
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_SRB_SHIFT 28
> +#define MIPI_RX_ANA18_CSI2A_RG_CSI2A_L1_EQ_SRB_MASK (0xf << 28)
> +#define MIPI_RX_ANA1C_CSI2A                                    0x401C
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_OS_CAL_EN_SHIFT 0
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_OS_CAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_MON_EN_SHIFT 1
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_MON_EN_MASK BIT(1)
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_SCA_SHIFT 2
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_SCA_MASK BIT(2)
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_SCB_SHIFT 3
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_SCB_MASK BIT(3)
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_IS_SHIFT 4
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_IS_MASK (0x3 << 4)
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_BW_SHIFT 6
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_BW_MASK (0x3 << 6)
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_SRA_SHIFT 8
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_SRA_MASK (0xf << 8)
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_SRB_SHIFT 12
> +#define MIPI_RX_ANA1C_CSI2A_RG_CSI2A_L2_EQ_SRB_MASK (0xf << 12)
> +#define MIPI_RX_ANA24_CSI2A                                    0x4024
> +#define MIPI_RX_ANA24_CSI2A_RG_CSI2A_RESERVE_SHIFT 24
> +#define MIPI_RX_ANA24_CSI2A_RG_CSI2A_RESERVE_MASK (0xff << 24)
> +#define MIPI_RX_ANA48_CSI2A                                    0x4048
> +#define MIPI_RX_ANA48_CSI2A_RGS_CSI2A_DPHY_L0_OS_CAL_CPLT_SHIFT 3
> +#define MIPI_RX_ANA48_CSI2A_RGS_CSI2A_DPHY_L0_OS_CAL_CPLT_MASK BIT(3)
> +#define MIPI_RX_ANA48_CSI2A_RGS_CSI2A_DPHY_L1_OS_CAL_CPLT_SHIFT 4
> +#define MIPI_RX_ANA48_CSI2A_RGS_CSI2A_DPHY_L1_OS_CAL_CPLT_MASK BIT(4)
> +#define MIPI_RX_ANA48_CSI2A_RGS_CSI2A_DPHY_L2_OS_CAL_CPLT_SHIFT 5
> +#define MIPI_RX_ANA48_CSI2A_RGS_CSI2A_DPHY_L2_OS_CAL_CPLT_MASK BIT(5)
> +#define MIPI_RX_ANA48_CSI2A_RGS_CSI2A_OS_CAL_CODE_SHIFT 8
> +#define MIPI_RX_ANA48_CSI2A_RGS_CSI2A_OS_CAL_CODE_MASK (0xff << 8)
> +#define MIPI_RX_WRAPPER80_CSI2A                                0x4080
> +#define MIPI_RX_WRAPPER80_CSI2A_CSR_CSI_CLK_MON_SHIFT 0
> +#define MIPI_RX_WRAPPER80_CSI2A_CSR_CSI_CLK_MON_MASK BIT(0)
> +#define MIPI_RX_WRAPPER80_CSI2A_CSR_CSI_MON_MUX_SHIFT 8
> +#define MIPI_RX_WRAPPER80_CSI2A_CSR_CSI_MON_MUX_MASK (0xff << 8)
> +#define MIPI_RX_WRAPPER80_CSI2A_CSR_CSI_RST_MODE_SHIFT 16
> +#define MIPI_RX_WRAPPER80_CSI2A_CSR_CSI_RST_MODE_MASK (0x3 << 16)
> +#define MIPI_RX_WRAPPER80_CSI2A_CSR_SW_RST_SHIFT 24
> +#define MIPI_RX_WRAPPER80_CSI2A_CSR_SW_RST_MASK (0xf << 24)
> +#define MIPI_RX_WRAPPER84_CSI2A                                0x4084
> +#define MIPI_RX_WRAPPER84_CSI2A_CSI_DEBUG_OUT_SHIFT 0
> +#define MIPI_RX_WRAPPER84_CSI2A_CSI_DEBUG_OUT_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER88_CSI2A                                0x4088
> +#define MIPI_RX_WRAPPER88_CSI2A_CSR_SW_MODE_0_SHIFT 0
> +#define MIPI_RX_WRAPPER88_CSI2A_CSR_SW_MODE_0_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER8C_CSI2A                                0x408C
> +#define MIPI_RX_WRAPPER8C_CSI2A_CSR_SW_MODE_1_SHIFT 0
> +#define MIPI_RX_WRAPPER8C_CSI2A_CSR_SW_MODE_1_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER90_CSI2A                                0x4090
> +#define MIPI_RX_WRAPPER90_CSI2A_CSR_SW_MODE_2_SHIFT 0
> +#define MIPI_RX_WRAPPER90_CSI2A_CSR_SW_MODE_2_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER94_CSI2A                                0x4094
> +#define MIPI_RX_WRAPPER94_CSI2A_CSR_SW_VALUE_0_SHIFT 0
> +#define MIPI_RX_WRAPPER94_CSI2A_CSR_SW_VALUE_0_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER98_CSI2A                                0x4098
> +#define MIPI_RX_WRAPPER98_CSI2A_CSR_SW_VALUE_1_SHIFT 0
> +#define MIPI_RX_WRAPPER98_CSI2A_CSR_SW_VALUE_1_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER9C_CSI2A                                0x409C
> +#define MIPI_RX_WRAPPER9C_CSI2A_CSR_SW_VALUE_2_SHIFT 0
> +#define MIPI_RX_WRAPPER9C_CSI2A_CSR_SW_VALUE_2_MASK (0xffffffff << 0)
> +#define MIPI_RX_ANAA4_CSI2A                                    0x40A4
> +#define MIPI_RX_ANAA4_CSI2A_RG_CSI2A_DPHY_L0_SYNC_INIT_SEL_SHIFT 0
> +#define MIPI_RX_ANAA4_CSI2A_RG_CSI2A_DPHY_L0_SYNC_INIT_SEL_MASK BIT(0)
> +#define MIPI_RX_ANAA4_CSI2A_RG_CSI2A_DPHY_L0_FORCE_INIT_SHIFT 1
> +#define MIPI_RX_ANAA4_CSI2A_RG_CSI2A_DPHY_L0_FORCE_INIT_MASK BIT(1)
> +#define MIPI_RX_ANAA4_CSI2A_RG_CSI2A_DPHY_L1_SYNC_INIT_SEL_SHIFT 2
> +#define MIPI_RX_ANAA4_CSI2A_RG_CSI2A_DPHY_L1_SYNC_INIT_SEL_MASK BIT(2)
> +#define MIPI_RX_ANAA4_CSI2A_RG_CSI2A_DPHY_L1_FORCE_INIT_SHIFT 3
> +#define MIPI_RX_ANAA4_CSI2A_RG_CSI2A_DPHY_L1_FORCE_INIT_MASK BIT(3)
> +#define MIPI_RX_ANAA4_CSI2A_RG_CSI2A_DPHY_L2_SYNC_INIT_SEL_SHIFT 4
> +#define MIPI_RX_ANAA4_CSI2A_RG_CSI2A_DPHY_L2_SYNC_INIT_SEL_MASK BIT(4)
> +#define MIPI_RX_ANAA4_CSI2A_RG_CSI2A_DPHY_L2_FORCE_INIT_SHIFT 5
> +#define MIPI_RX_ANAA4_CSI2A_RG_CSI2A_DPHY_L2_FORCE_INIT_MASK BIT(5)
> +#define MIPI_RX_ANAA8_CSI2A                                    0x40A8
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_DPHY_L0_BYTECK_INVERT_SHIFT 0
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_DPHY_L0_BYTECK_INVERT_MASK BIT(0)
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_DPHY_L1_BYTECK_INVERT_SHIFT 1
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_DPHY_L1_BYTECK_INVERT_MASK BIT(1)
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_DPHY_L2_BYTECK_INVERT_SHIFT 2
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_DPHY_L2_BYTECK_INVERT_MASK BIT(2)
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_DPHY_HSDET_LEVEL_MODE_EN_SHIFT 3
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_DPHY_HSDET_LEVEL_MODE_EN_MASK BIT(3)
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_OS_CAL_SEL_SHIFT 4
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_OS_CAL_SEL_MASK (0x7 << 4)
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_DPHY_HSDET_DIG_BACK_EN_SHIFT 7
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_DPHY_HSDET_DIG_BACK_EN_MASK BIT(7)
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_DPHY_DELAYCAL_CK_SEL_SHIFT 8
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_DPHY_DELAYCAL_CK_SEL_MASK (0x7 << 8)
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_OS_CAL_DIV_SHIFT 11
> +#define MIPI_RX_ANAA8_CSI2A_RG_CSI2A_OS_CAL_DIV_MASK (0x3 << 11)
> +#define MIPI_RX_ANA00_CSI2B                                    0x5000
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_EQ_PROTECT_EN_SHIFT 1
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_EQ_PROTECT_EN_MASK BIT(1)
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_BG_LPF_EN_SHIFT 2
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_BG_LPF_EN_MASK BIT(2)
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_BG_CORE_EN_SHIFT 3
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_BG_CORE_EN_MASK BIT(3)
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_DPHY_L0_CKMODE_EN_SHIFT 5
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_DPHY_L0_CKMODE_EN_MASK BIT(5)
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_DPHY_L0_CKSEL_SHIFT 6
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_DPHY_L0_CKSEL_MASK BIT(6)
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_DPHY_L1_CKMODE_EN_SHIFT 8
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_DPHY_L1_CKMODE_EN_MASK BIT(8)
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_DPHY_L1_CKSEL_SHIFT 9
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_DPHY_L1_CKSEL_MASK BIT(9)
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_DPHY_L2_CKMODE_EN_SHIFT 11
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_DPHY_L2_CKMODE_EN_MASK BIT(11)
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_DPHY_L2_CKSEL_SHIFT 12
> +#define MIPI_RX_ANA00_CSI2B_RG_CSI2B_DPHY_L2_CKSEL_MASK BIT(12)
> +#define MIPI_RX_ANA04_CSI2B                                    0x5004
> +#define MIPI_RX_ANA04_CSI2B_RG_CSI2B_BG_LPRX_VTH_SEL_SHIFT 0
> +#define MIPI_RX_ANA04_CSI2B_RG_CSI2B_BG_LPRX_VTH_SEL_MASK (0x7 << 0)
> +#define MIPI_RX_ANA04_CSI2B_RG_CSI2B_BG_LPRX_VTL_SEL_SHIFT 4
> +#define MIPI_RX_ANA04_CSI2B_RG_CSI2B_BG_LPRX_VTL_SEL_MASK (0x7 << 4)
> +#define MIPI_RX_ANA04_CSI2B_RG_CSI2B_BG_HSDET_VTH_SEL_SHIFT 8
> +#define MIPI_RX_ANA04_CSI2B_RG_CSI2B_BG_HSDET_VTH_SEL_MASK (0x7 << 8)
> +#define MIPI_RX_ANA04_CSI2B_RG_CSI2B_BG_HSDET_VTL_SEL_SHIFT 12
> +#define MIPI_RX_ANA04_CSI2B_RG_CSI2B_BG_HSDET_VTL_SEL_MASK (0x7 << 12)
> +#define MIPI_RX_ANA04_CSI2B_RG_CSI2B_BG_VREF_SEL_SHIFT 16
> +#define MIPI_RX_ANA04_CSI2B_RG_CSI2B_BG_VREF_SEL_MASK (0xf << 16)
> +#define MIPI_RX_ANA04_CSI2B_RG_CSI2B_BG_MON_VREF_SEL_SHIFT 24
> +#define MIPI_RX_ANA04_CSI2B_RG_CSI2B_BG_MON_VREF_SEL_MASK (0xf << 24)
> +#define MIPI_RX_ANA04_CSI2B_RG_CSI2B_FORCE_HSRT_EN_SHIFT 28
> +#define MIPI_RX_ANA04_CSI2B_RG_CSI2B_FORCE_HSRT_EN_MASK BIT(28)
> +#define MIPI_RX_ANA08_CSI2B                                    0x5008
> +#define MIPI_RX_ANA08_CSI2B_RG_CSI2B_L0P_HSRT_CODE_SHIFT 0
> +#define MIPI_RX_ANA08_CSI2B_RG_CSI2B_L0P_HSRT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA08_CSI2B_RG_CSI2B_L0N_HSRT_CODE_SHIFT 8
> +#define MIPI_RX_ANA08_CSI2B_RG_CSI2B_L0N_HSRT_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA08_CSI2B_RG_CSI2B_L1P_HSRT_CODE_SHIFT 16
> +#define MIPI_RX_ANA08_CSI2B_RG_CSI2B_L1P_HSRT_CODE_MASK (0x1f << 16)
> +#define MIPI_RX_ANA08_CSI2B_RG_CSI2B_L1N_HSRT_CODE_SHIFT 24
> +#define MIPI_RX_ANA08_CSI2B_RG_CSI2B_L1N_HSRT_CODE_MASK (0x1f << 24)
> +#define MIPI_RX_ANA0C_CSI2B                                    0x500C
> +#define MIPI_RX_ANA0C_CSI2B_RG_CSI2B_L2P_HSRT_CODE_SHIFT 0
> +#define MIPI_RX_ANA0C_CSI2B_RG_CSI2B_L2P_HSRT_CODE_MASK (0x1f << 0)
> +#define MIPI_RX_ANA0C_CSI2B_RG_CSI2B_L2N_HSRT_CODE_SHIFT 8
> +#define MIPI_RX_ANA0C_CSI2B_RG_CSI2B_L2N_HSRT_CODE_MASK (0x1f << 8)
> +#define MIPI_RX_ANA10_CSI2B                                    0x5010
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L0_DELAYCAL_EN_SHIFT 0
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L0_DELAYCAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L0_DELAYCAL_RSTB_SHIFT 1
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L0_DELAYCAL_RSTB_MASK BIT(1)
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L0_VREF_SEL_SHIFT 2
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L0_VREF_SEL_MASK (0x3f << 2)
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L1_DELAYCAL_EN_SHIFT 8
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L1_DELAYCAL_EN_MASK BIT(8)
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L1_DELAYCAL_RSTB_SHIFT 9
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L1_DELAYCAL_RSTB_MASK BIT(9)
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L1_VREF_SEL_SHIFT 10
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L1_VREF_SEL_MASK (0x3f << 10)
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L2_DELAYCAL_EN_SHIFT 16
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L2_DELAYCAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L2_DELAYCAL_RSTB_SHIFT 17
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L2_DELAYCAL_RSTB_MASK BIT(17)
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L2_VREF_SEL_SHIFT 18
> +#define MIPI_RX_ANA10_CSI2B_RG_CSI2B_DPHY_L2_VREF_SEL_MASK (0x3f << 18)
> +#define MIPI_RX_ANA18_CSI2B                                    0x5018
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_OS_CAL_EN_SHIFT 0
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_OS_CAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_MON_EN_SHIFT 1
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_MON_EN_MASK BIT(1)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_SCA_SHIFT 2
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_SCA_MASK BIT(2)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_SCB_SHIFT 3
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_SCB_MASK BIT(3)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_IS_SHIFT 4
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_IS_MASK (0x3 << 4)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_BW_SHIFT 6
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_BW_MASK (0x3 << 6)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_SRA_SHIFT 8
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_SRA_MASK (0xf << 8)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_SRB_SHIFT 12
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L0_EQ_SRB_MASK (0xf << 12)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_OS_CAL_EN_SHIFT 16
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_OS_CAL_EN_MASK BIT(16)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_MON_EN_SHIFT 17
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_MON_EN_MASK BIT(17)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_SCA_SHIFT 18
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_SCA_MASK BIT(18)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_SCB_SHIFT 19
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_SCB_MASK BIT(19)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_IS_SHIFT 20
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_IS_MASK (0x3 << 20)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_BW_SHIFT 22
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_BW_MASK (0x3 << 22)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_SRA_SHIFT 24
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_SRA_MASK (0xf << 24)
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_SRB_SHIFT 28
> +#define MIPI_RX_ANA18_CSI2B_RG_CSI2B_L1_EQ_SRB_MASK (0xf << 28)
> +#define MIPI_RX_ANA1C_CSI2B                                    0x501C
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_OS_CAL_EN_SHIFT 0
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_OS_CAL_EN_MASK BIT(0)
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_MON_EN_SHIFT 1
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_MON_EN_MASK BIT(1)
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_SCA_SHIFT 2
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_SCA_MASK BIT(2)
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_SCB_SHIFT 3
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_SCB_MASK BIT(3)
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_IS_SHIFT 4
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_IS_MASK (0x3 << 4)
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_BW_SHIFT 6
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_BW_MASK (0x3 << 6)
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_SRA_SHIFT 8
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_SRA_MASK (0xf << 8)
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_SRB_SHIFT 12
> +#define MIPI_RX_ANA1C_CSI2B_RG_CSI2B_L2_EQ_SRB_MASK (0xf << 12)
> +#define MIPI_RX_ANA24_CSI2B                                    0x5024
> +#define MIPI_RX_ANA24_CSI2B_RG_CSI2B_RESERVE_SHIFT 24
> +#define MIPI_RX_ANA24_CSI2B_RG_CSI2B_RESERVE_MASK (0xff << 24)
> +#define MIPI_RX_ANA48_CSI2B                                    0x5048
> +#define MIPI_RX_ANA48_CSI2B_RGS_CSI2B_DPHY_L0_OS_CAL_CPLT_SHIFT 3
> +#define MIPI_RX_ANA48_CSI2B_RGS_CSI2B_DPHY_L0_OS_CAL_CPLT_MASK BIT(3)
> +#define MIPI_RX_ANA48_CSI2B_RGS_CSI2B_DPHY_L1_OS_CAL_CPLT_SHIFT 4
> +#define MIPI_RX_ANA48_CSI2B_RGS_CSI2B_DPHY_L1_OS_CAL_CPLT_MASK BIT(4)
> +#define MIPI_RX_ANA48_CSI2B_RGS_CSI2B_DPHY_L2_OS_CAL_CPLT_SHIFT 5
> +#define MIPI_RX_ANA48_CSI2B_RGS_CSI2B_DPHY_L2_OS_CAL_CPLT_MASK BIT(5)
> +#define MIPI_RX_ANA48_CSI2B_RGS_CSI2B_OS_CAL_CODE_SHIFT 8
> +#define MIPI_RX_ANA48_CSI2B_RGS_CSI2B_OS_CAL_CODE_MASK (0xff << 8)
> +#define MIPI_RX_WRAPPER80_CSI2B                                0x5080
> +#define MIPI_RX_WRAPPER80_CSI2B_CSR_CSI_CLK_MON_SHIFT 0
> +#define MIPI_RX_WRAPPER80_CSI2B_CSR_CSI_CLK_MON_MASK BIT(0)
> +#define MIPI_RX_WRAPPER80_CSI2B_CSR_CSI_MON_MUX_SHIFT 8
> +#define MIPI_RX_WRAPPER80_CSI2B_CSR_CSI_MON_MUX_MASK (0xff << 8)
> +#define MIPI_RX_WRAPPER80_CSI2B_CSR_CSI_RST_MODE_SHIFT 16
> +#define MIPI_RX_WRAPPER80_CSI2B_CSR_CSI_RST_MODE_MASK (0x3 << 16)
> +#define MIPI_RX_WRAPPER80_CSI2B_CSR_SW_RST_SHIFT 24
> +#define MIPI_RX_WRAPPER80_CSI2B_CSR_SW_RST_MASK (0xf << 24)
> +#define MIPI_RX_WRAPPER84_CSI2B                                0x5084
> +#define MIPI_RX_WRAPPER84_CSI2B_CSI_DEBUG_OUT_SHIFT 0
> +#define MIPI_RX_WRAPPER84_CSI2B_CSI_DEBUG_OUT_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER88_CSI2B                                0x5088
> +#define MIPI_RX_WRAPPER88_CSI2B_CSR_SW_MODE_0_SHIFT 0
> +#define MIPI_RX_WRAPPER88_CSI2B_CSR_SW_MODE_0_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER8C_CSI2B                                0x508C
> +#define MIPI_RX_WRAPPER8C_CSI2B_CSR_SW_MODE_1_SHIFT 0
> +#define MIPI_RX_WRAPPER8C_CSI2B_CSR_SW_MODE_1_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER90_CSI2B                                0x5090
> +#define MIPI_RX_WRAPPER90_CSI2B_CSR_SW_MODE_2_SHIFT 0
> +#define MIPI_RX_WRAPPER90_CSI2B_CSR_SW_MODE_2_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER94_CSI2B                                0x5094
> +#define MIPI_RX_WRAPPER94_CSI2B_CSR_SW_VALUE_0_SHIFT 0
> +#define MIPI_RX_WRAPPER94_CSI2B_CSR_SW_VALUE_0_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER98_CSI2B                                0x5098
> +#define MIPI_RX_WRAPPER98_CSI2B_CSR_SW_VALUE_1_SHIFT 0
> +#define MIPI_RX_WRAPPER98_CSI2B_CSR_SW_VALUE_1_MASK (0xffffffff << 0)
> +#define MIPI_RX_WRAPPER9C_CSI2B                                0x509C
> +#define MIPI_RX_WRAPPER9C_CSI2B_CSR_SW_VALUE_2_SHIFT 0
> +#define MIPI_RX_WRAPPER9C_CSI2B_CSR_SW_VALUE_2_MASK (0xffffffff << 0)
> +#define MIPI_RX_ANAA4_CSI2B                                    0x50A4
> +#define MIPI_RX_ANAA4_CSI2B_RG_CSI2B_DPHY_L0_SYNC_INIT_SEL_SHIFT 0
> +#define MIPI_RX_ANAA4_CSI2B_RG_CSI2B_DPHY_L0_SYNC_INIT_SEL_MASK BIT(0)
> +#define MIPI_RX_ANAA4_CSI2B_RG_CSI2B_DPHY_L0_FORCE_INIT_SHIFT 1
> +#define MIPI_RX_ANAA4_CSI2B_RG_CSI2B_DPHY_L0_FORCE_INIT_MASK BIT(1)
> +#define MIPI_RX_ANAA4_CSI2B_RG_CSI2B_DPHY_L1_SYNC_INIT_SEL_SHIFT 2
> +#define MIPI_RX_ANAA4_CSI2B_RG_CSI2B_DPHY_L1_SYNC_INIT_SEL_MASK BIT(2)
> +#define MIPI_RX_ANAA4_CSI2B_RG_CSI2B_DPHY_L1_FORCE_INIT_SHIFT 3
> +#define MIPI_RX_ANAA4_CSI2B_RG_CSI2B_DPHY_L1_FORCE_INIT_MASK BIT(3)
> +#define MIPI_RX_ANAA4_CSI2B_RG_CSI2B_DPHY_L2_SYNC_INIT_SEL_SHIFT 4
> +#define MIPI_RX_ANAA4_CSI2B_RG_CSI2B_DPHY_L2_SYNC_INIT_SEL_MASK BIT(4)
> +#define MIPI_RX_ANAA4_CSI2B_RG_CSI2B_DPHY_L2_FORCE_INIT_SHIFT 5
> +#define MIPI_RX_ANAA4_CSI2B_RG_CSI2B_DPHY_L2_FORCE_INIT_MASK BIT(5)
> +#define MIPI_RX_ANAA8_CSI2B                                    0x50A8
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_DPHY_L0_BYTECK_INVERT_SHIFT 0
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_DPHY_L0_BYTECK_INVERT_MASK BIT(0)
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_DPHY_L1_BYTECK_INVERT_SHIFT 1
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_DPHY_L1_BYTECK_INVERT_MASK BIT(1)
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_DPHY_L2_BYTECK_INVERT_SHIFT 2
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_DPHY_L2_BYTECK_INVERT_MASK BIT(2)
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_DPHY_HSDET_LEVEL_MODE_EN_SHIFT 3
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_DPHY_HSDET_LEVEL_MODE_EN_MASK BIT(3)
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_OS_CAL_SEL_SHIFT 4
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_OS_CAL_SEL_MASK (0x7 << 4)
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_DPHY_HSDET_DIG_BACK_EN_SHIFT 7
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_DPHY_HSDET_DIG_BACK_EN_MASK BIT(7)
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_DPHY_DELAYCAL_CK_SEL_SHIFT 8
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_DPHY_DELAYCAL_CK_SEL_MASK (0x7 << 8)
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_OS_CAL_DIV_SHIFT 11
> +#define MIPI_RX_ANAA8_CSI2B_RG_CSI2B_OS_CAL_DIV_MASK (0x3 << 11)

All the register definition of CSI0A, CSI0B, CSI1A, CSI1B, CSI2A,
CSI2B are all the same. I think you could use only one definition with
six different offset for these registers, so we could reduce these
repeated definition.

Regards,
Chun-Kuang.

> +
> +#endif
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

Chun-Kuang Hu April 13, 2020, 9:27 a.m. UTC | #3

Hi, Louis:

Louis Kuo (郭德寧) <louis.kuo@mediatek.com> 於 2020年4月13日 週一 上午10:04寫道：
>
> Hi Chun-Kuang,
>
> The comment you mentioned,
> I think the phy control part should be placed in drivers/phy/mediatek/. In [1], device csis point to a device mipi_phy.
> csis' driver is in [2], and mipi_phy's driver is in [3]
>
> I reply as below,
> =>
> Since Seninf module includes mipi-csi phy, top mux, mux ctrl parts, combine all together into a v4l2-subdev
> linking with v4l2 sensor drivers and v4l2 ISP driver backward and forward to transmit and process image.
>

It  seems that seninf is a mfd or syscon device. MMSYS  [1] is a
system controller which control multiple functions. Its major driver
is placed in [2], and its clock control function is placed in [3].

[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt?h=next-20200413
[2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/soc/mediatek/mtk-mmsys.c?h=next-20200413
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/clk/mediatek/clk-mt8173-mm.c?h=next-20200413

> The data lanes and port settings is configured by v4l2 sensor drivers,
> For control reason, it's a better way to let seninf mipi-csi part inside seninf v4l2-subdev rather than an independent phy device in drivers/phy/mediatek
>
> There have similar design in omap4iss and Rkisp1-isp driver, they all in staging step.
> https://elixir.bootlin.com/linux/v5.6/source/drivers/staging/media/rkisp1
> https://elixir.bootlin.com/linux/v5.6/source/drivers/staging/media/omap4iss

Staging driver means there are some things need to modify to move out
of staging folder, so I think this is not a strong reason to keep phy
control in drivers/media/ folder. You could move this driver to
drivers/staging/media/ folder and I would have no comment about this.

Regards,
Chun-Kuang.

>
> BRs
> Louis
>
> -----Original Message-----
> From: Chun-Kuang Hu [mailto:chunkuang.hu@kernel.org]
> Sent: Saturday, April 11, 2020 8:17 AM
> To: Louis Kuo (郭德寧) <louis.kuo@mediatek.com>
> Cc: hans.verkuil@cisco.com; laurent.pinchart+renesas@ideasonboard.com; tfiga@chromium.org; keiichiw@chromium.org; Matthias Brugger <matthias.bgg@gmail.com>; Mauro Carvalho Chehab <mchehab@kernel.org>; devicetree@vger.kernel.org; Sean Cheng (鄭昇弘) <Sean.Cheng@mediatek.com>; srv_heupstream <srv_heupstream@mediatek.com>; Jerry-ch Chen (陳敬憲) <Jerry-ch.Chen@mediatek.com>; Jungo Lin (林明俊) <jungo.lin@mediatek.com>; Sj Huang (黃信璋) <sj.huang@mediatek.com>; yuzhao@chromium.org; moderated list:ARM/Mediatek SoC support <linux-mediatek@lists.infradead.org>; zwisler@chromium.org; Christie Yu (游雅惠) <christie.yu@mediatek.com>; Frederic Chen (陳俊元) <Frederic.Chen@mediatek.com>; Linux ARM <linux-arm-kernel@lists.infradead.org>; linux-media@vger.kernel.org
> Subject: Re: [RFC PATCH V6 1/3] media: platform: mtk-isp: Add Mediatek sensor interface driver
>
> Hi, Louis:
>
> Louis Kuo <louis.kuo@mediatek.com> 於 2020年4月10日 週五 下午3:18寫道：
> >
> > This patch adds Mediatek's sensor interface driver. Sensor interface
> > driver is a MIPI-CSI2 host driver, namely, a HW camera interface
> > controller. It support a widely adopted, simple, high-speed protocol
> > primarily intended for point-to-point image and video transmission
> > between cameras and host devices. The mtk-isp directory will contain
> > drivers for multiple IP blocks found in Mediatek ISP system. It will
> > include ISP Pass 1 driver, sensor interface driver, DIP driver and face detection driver.
> >
> > Signed-off-by: Louis Kuo <louis.kuo@mediatek.com>
> > ---
> >  drivers/media/platform/Makefile               |    1 +
> >  drivers/media/platform/mtk-isp/Kconfig        |   18 +
> >  drivers/media/platform/mtk-isp/Makefile       |    3 +
> >  .../media/platform/mtk-isp/seninf/Makefile    |    5 +
> >  drivers/media/platform/mtk-isp/seninf/TODO    |   18 +
> >  .../platform/mtk-isp/seninf/mtk_seninf.c      | 1173 +++++++++++++
> >  .../platform/mtk-isp/seninf/mtk_seninf_reg.h  | 1491 +++++++++++++++++
> >  .../mtk-isp/seninf/mtk_seninf_rx_reg.h        | 1398 ++++++++++++++++
> >  8 files changed, 4107 insertions(+)
> >  create mode 100644 drivers/media/platform/mtk-isp/Kconfig
> >  create mode 100644 drivers/media/platform/mtk-isp/Makefile
> >  create mode 100644 drivers/media/platform/mtk-isp/seninf/Makefile
> >  create mode 100644 drivers/media/platform/mtk-isp/seninf/TODO
> >  create mode 100644 drivers/media/platform/mtk-isp/seninf/mtk_seninf.c
> >  create mode 100644
> > drivers/media/platform/mtk-isp/seninf/mtk_seninf_reg.h
> >  create mode 100644
> > drivers/media/platform/mtk-isp/seninf/mtk_seninf_rx_reg.h
> >
>
> [snip]
>
> > +
> > +static void mtk_seninf_set_dphy(struct mtk_seninf *priv, unsigned int
> > +seninf) {
> > +       void __iomem *pmipi_rx_base = priv->csi2_rx[CFG_CSI_PORT_0];
> > +       unsigned int port = priv->port;
> > +       void __iomem *pmipi_rx = priv->csi2_rx[port];
> > +       void __iomem *pmipi_rx_conf = priv->base + 0x1000 * seninf;
> > +
> > +       /* Set analog phy mode to DPHY */
> > +       if (is_cdphy_combo(port))
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A, RG_CSI0A_CPHY_EN, 0);
> > +       /* 4D1C: MIPIRX_ANALOG_A_BASE = 0x00001A42 */
> > +       if (is_4d1c(port)) {
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > +                           RG_CSI0A_DPHY_L0_CKMODE_EN, 0);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > +                           RG_CSI0A_DPHY_L0_CKSEL, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > +                           RG_CSI0A_DPHY_L1_CKMODE_EN, 0);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > +                           RG_CSI0A_DPHY_L1_CKSEL, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > +                           RG_CSI0A_DPHY_L2_CKMODE_EN, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > +                           RG_CSI0A_DPHY_L2_CKSEL, 1);
> > +       } else {/* MIPIRX_ANALOG_BASE = 0x102 */
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > +                           RG_CSI0A_DPHY_L0_CKMODE_EN, 0);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > +                           RG_CSI0A_DPHY_L0_CKSEL, 0);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > +                           RG_CSI0A_DPHY_L1_CKMODE_EN, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > +                           RG_CSI0A_DPHY_L1_CKSEL, 0);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > +                           RG_CSI0A_DPHY_L2_CKMODE_EN, 0);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > +                           RG_CSI0A_DPHY_L2_CKSEL, 0);
> > +       }
> > +       if (is_cdphy_combo(port))
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > + RG_CSI0B_CPHY_EN, 0);
> > +
> > +       /* Only 4d1c need set CSIB: MIPIRX_ANALOG_B_BASE = 0x00001242 */
> > +       if (is_4d1c(port)) {
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > +                           RG_CSI0B_DPHY_L0_CKMODE_EN, 0);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > +                           RG_CSI0B_DPHY_L0_CKSEL, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > +                           RG_CSI0B_DPHY_L1_CKMODE_EN, 0);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > +                           RG_CSI0B_DPHY_L1_CKSEL, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > +                           RG_CSI0B_DPHY_L2_CKMODE_EN, 0);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > +                           RG_CSI0B_DPHY_L2_CKSEL, 1);
> > +       } else {/* MIPIRX_ANALOG_BASE = 0x102 */
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > +                           RG_CSI0B_DPHY_L0_CKSEL, 0);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > +                           RG_CSI0B_DPHY_L1_CKMODE_EN, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > +                           RG_CSI0B_DPHY_L1_CKSEL, 0);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > +                           RG_CSI0B_DPHY_L2_CKMODE_EN, 0);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > +                           RG_CSI0B_DPHY_L2_CKSEL, 0);
> > +       }
> > +       /* Byte clock invert */
> > +       SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0A,
> > +                   RG_CSI0A_CDPHY_L0_T0_BYTECK_INVERT, 1);
> > +       SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0A,
> > +                   RG_CSI0A_DPHY_L1_BYTECK_INVERT, 1);
> > +       SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0A,
> > +                   RG_CSI0A_CDPHY_L2_T1_BYTECK_INVERT, 1);
> > +
> > +       if (is_4d1c(port)) {
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0B,
> > +                           RG_CSI0B_CDPHY_L0_T0_BYTECK_INVERT, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0B,
> > +                           RG_CSI0B_DPHY_L1_BYTECK_INVERT, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0B,
> > +                           RG_CSI0B_CDPHY_L2_T1_BYTECK_INVERT, 1);
> > +       }
> > +
> > +       /* Start ANA EQ tuning */
> > +       if (is_cdphy_combo(port)) {
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0A,
> > +                           RG_CSI0A_L0_T0AB_EQ_IS, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0A,
> > +                           RG_CSI0A_L0_T0AB_EQ_BW, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0A,
> > +                           RG_CSI0A_L1_T1AB_EQ_IS, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0A,
> > +                           RG_CSI0A_L1_T1AB_EQ_BW, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0A,
> > +                           RG_CSI0A_L2_T1BC_EQ_IS, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0A,
> > +                           RG_CSI0A_L2_T1BC_EQ_BW, 1);
> > +
> > +               if (is_4d1c(port)) { /* 4d1c */
> > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0B,
> > +                                   RG_CSI0B_L0_T0AB_EQ_IS, 1);
> > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0B,
> > +                                   RG_CSI0B_L0_T0AB_EQ_BW, 1);
> > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0B,
> > +                                   RG_CSI0B_L1_T1AB_EQ_IS, 1);
> > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0B,
> > +                                   RG_CSI0B_L1_T1AB_EQ_BW, 1);
> > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0B,
> > +                                   RG_CSI0B_L2_T1BC_EQ_IS, 1);
> > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0B,
> > +                                   RG_CSI0B_L2_T1BC_EQ_BW, 1);
> > +               }
> > +       } else {
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
> > +                           RG_CSI1A_L0_EQ_IS, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
> > +                           RG_CSI1A_L0_EQ_BW, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
> > +                           RG_CSI1A_L1_EQ_IS, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
> > +                           RG_CSI1A_L1_EQ_BW, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1A,
> > +                           RG_CSI1A_L2_EQ_IS, 1);
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1A,
> > +                           RG_CSI1A_L2_EQ_BW, 1);
> > +
> > +               if (is_4d1c(port)) { /* 4d1c */
> > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
> > +                                   RG_CSI1B_L0_EQ_IS, 1);
> > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
> > +                                   RG_CSI1B_L0_EQ_BW, 1);
> > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
> > +                                   RG_CSI1B_L1_EQ_IS, 1);
> > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
> > +                                   RG_CSI1B_L1_EQ_BW, 1);
> > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1B,
> > +                                   RG_CSI1B_L2_EQ_IS, 1);
> > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1B,
> > +                                   RG_CSI1B_L2_EQ_BW, 1);
> > +               }
> > +       }
> > +
> > +       /* End ANA EQ tuning */
> > +       writel(0x90, pmipi_rx_base + MIPI_RX_ANA40_CSI0A);
> > +       SENINF_BITS(pmipi_rx, MIPI_RX_ANA24_CSI0A,
> > +                   RG_CSI0A_RESERVE, 0x40);
> > +       if (is_4d1c(port))
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA24_CSI0B,
> > +                           RG_CSI0B_RESERVE, 0x40);
> > +       SENINF_BITS(pmipi_rx, MIPI_RX_WRAPPER80_CSI0A,
> > +                   CSR_CSI_RST_MODE, 0);
> > +       if (is_4d1c(port))
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_WRAPPER80_CSI0B,
> > +                           CSR_CSI_RST_MODE, 0);
> > +       /* ANA power on */
> > +       SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > +                   RG_CSI0A_BG_CORE_EN, 1);
> > +       if (is_4d1c(port))
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > +                           RG_CSI0B_BG_CORE_EN, 1);
> > +       usleep_range(20, 40);
> > +       SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > +                   RG_CSI0A_BG_LPF_EN, 1);
> > +       if (is_4d1c(port))
> > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > +                           RG_CSI0B_BG_LPF_EN, 1);
> > +
> > +       udelay(1);
> > +       /* 4d1c: MIPIRX_CONFIG_CSI_BASE = 0xC9000000; */
> > +       if (is_4d1c(port)) {
> > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > +                           CSI0_BIST_LN0_MUX, 1);
> > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > +                           CSI0_BIST_LN1_MUX, 2);
> > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > +                           CSI0_BIST_LN2_MUX, 0);
> > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > +                           CSI0_BIST_LN3_MUX, 3);
> > +       } else { /* 2d1c: MIPIRX_CONFIG_CSI_BASE = 0xE4000000; */
> > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > +                           CSI0_BIST_LN0_MUX, 0);
> > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > +                           CSI0_BIST_LN1_MUX, 1);
> > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > +                           CSI0_BIST_LN2_MUX, 2);
> > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > +                           CSI0_BIST_LN3_MUX, 3);
> > +       }
> > +}
>
> I think the phy control part should be placed in drivers/phy/mediatek/. In [1], device csis point to a device mipi_phy.
> csis' driver is in [2], and mipi_phy's driver is in [3]
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/exynos4.dtsi?h=v5.6
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/media/platform/exynos4-is/mipi-csis.c?h=v5.6
> [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/phy/samsung/phy-exynos-mipi-video.c?h=v5.6
>
> Regards,
> Chun-Kuang.

Helen Mae Koike Fornazier April 13, 2020, 8:45 p.m. UTC | #4

On 4/13/20 6:27 AM, Chun-Kuang Hu wrote:
> Hi, Louis:
> 
> Louis Kuo (郭德寧) <louis.kuo@mediatek.com> 於 2020年4月13日 週一 上午10:04寫道：
>>
>> Hi Chun-Kuang,
>>
>> The comment you mentioned,
>> I think the phy control part should be placed in drivers/phy/mediatek/. In [1], device csis point to a device mipi_phy.
>> csis' driver is in [2], and mipi_phy's driver is in [3]
>>
>> I reply as below,
>> =>
>> Since Seninf module includes mipi-csi phy, top mux, mux ctrl parts, combine all together into a v4l2-subdev
>> linking with v4l2 sensor drivers and v4l2 ISP driver backward and forward to transmit and process image.
>>
> 
> It  seems that seninf is a mfd or syscon device. MMSYS  [1] is a
> system controller which control multiple functions. Its major driver
> is placed in [2], and its clock control function is placed in [3].
> 
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt?h=next-20200413
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/soc/mediatek/mtk-mmsys.c?h=next-20200413
> [3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/clk/mediatek/clk-mt8173-mm.c?h=next-20200413
> 
>> The data lanes and port settings is configured by v4l2 sensor drivers,
>> For control reason, it's a better way to let seninf mipi-csi part inside seninf v4l2-subdev rather than an independent phy device in drivers/phy/mediatek
>>
>> There have similar design in omap4iss and Rkisp1-isp driver, they all in staging step.
>> https://elixir.bootlin.com/linux/v5.6/source/drivers/staging/media/rkisp1

fyi, the rkisp1 driver doesn't have the mipi dphy part inside it, we have
phy-rockchip-dphy-rx0, that should be moved to drivers/phy/ soon.

https://elixir.bootlin.com/linux/v5.6/source/drivers/staging/media/phy-rockchip-dphy-rx0

Regards,
Helen

>> https://elixir.bootlin.com/linux/v5.6/source/drivers/staging/media/omap4iss
> 
> Staging driver means there are some things need to modify to move out
> of staging folder, so I think this is not a strong reason to keep phy
> control in drivers/media/ folder. You could move this driver to
> drivers/staging/media/ folder and I would have no comment about this.
> 
> Regards,
> Chun-Kuang.
> 
>>
>> BRs
>> Louis
>>
>> -----Original Message-----
>> From: Chun-Kuang Hu [mailto:chunkuang.hu@kernel.org]
>> Sent: Saturday, April 11, 2020 8:17 AM
>> To: Louis Kuo (郭德寧) <louis.kuo@mediatek.com>
>> Cc: hans.verkuil@cisco.com; laurent.pinchart+renesas@ideasonboard.com; tfiga@chromium.org; keiichiw@chromium.org; Matthias Brugger <matthias.bgg@gmail.com>; Mauro Carvalho Chehab <mchehab@kernel.org>; devicetree@vger.kernel.org; Sean Cheng (鄭昇弘) <Sean.Cheng@mediatek.com>; srv_heupstream <srv_heupstream@mediatek.com>; Jerry-ch Chen (陳敬憲) <Jerry-ch.Chen@mediatek.com>; Jungo Lin (林明俊) <jungo.lin@mediatek.com>; Sj Huang (黃信璋) <sj.huang@mediatek.com>; yuzhao@chromium.org; moderated list:ARM/Mediatek SoC support <linux-mediatek@lists.infradead.org>; zwisler@chromium.org; Christie Yu (游雅惠) <christie.yu@mediatek.com>; Frederic Chen (陳俊元) <Frederic.Chen@mediatek.com>; Linux ARM <linux-arm-kernel@lists.infradead.org>; linux-media@vger.kernel.org
>> Subject: Re: [RFC PATCH V6 1/3] media: platform: mtk-isp: Add Mediatek sensor interface driver
>>
>> Hi, Louis:
>>
>> Louis Kuo <louis.kuo@mediatek.com> 於 2020年4月10日 週五 下午3:18寫道：
>>>
>>> This patch adds Mediatek's sensor interface driver. Sensor interface
>>> driver is a MIPI-CSI2 host driver, namely, a HW camera interface
>>> controller. It support a widely adopted, simple, high-speed protocol
>>> primarily intended for point-to-point image and video transmission
>>> between cameras and host devices. The mtk-isp directory will contain
>>> drivers for multiple IP blocks found in Mediatek ISP system. It will
>>> include ISP Pass 1 driver, sensor interface driver, DIP driver and face detection driver.
>>>
>>> Signed-off-by: Louis Kuo <louis.kuo@mediatek.com>
>>> ---
>>>  drivers/media/platform/Makefile               |    1 +
>>>  drivers/media/platform/mtk-isp/Kconfig        |   18 +
>>>  drivers/media/platform/mtk-isp/Makefile       |    3 +
>>>  .../media/platform/mtk-isp/seninf/Makefile    |    5 +
>>>  drivers/media/platform/mtk-isp/seninf/TODO    |   18 +
>>>  .../platform/mtk-isp/seninf/mtk_seninf.c      | 1173 +++++++++++++
>>>  .../platform/mtk-isp/seninf/mtk_seninf_reg.h  | 1491 +++++++++++++++++
>>>  .../mtk-isp/seninf/mtk_seninf_rx_reg.h        | 1398 ++++++++++++++++
>>>  8 files changed, 4107 insertions(+)
>>>  create mode 100644 drivers/media/platform/mtk-isp/Kconfig
>>>  create mode 100644 drivers/media/platform/mtk-isp/Makefile
>>>  create mode 100644 drivers/media/platform/mtk-isp/seninf/Makefile
>>>  create mode 100644 drivers/media/platform/mtk-isp/seninf/TODO
>>>  create mode 100644 drivers/media/platform/mtk-isp/seninf/mtk_seninf.c
>>>  create mode 100644
>>> drivers/media/platform/mtk-isp/seninf/mtk_seninf_reg.h
>>>  create mode 100644
>>> drivers/media/platform/mtk-isp/seninf/mtk_seninf_rx_reg.h
>>>
>>
>> [snip]
>>
>>> +
>>> +static void mtk_seninf_set_dphy(struct mtk_seninf *priv, unsigned int
>>> +seninf) {
>>> +       void __iomem *pmipi_rx_base = priv->csi2_rx[CFG_CSI_PORT_0];
>>> +       unsigned int port = priv->port;
>>> +       void __iomem *pmipi_rx = priv->csi2_rx[port];
>>> +       void __iomem *pmipi_rx_conf = priv->base + 0x1000 * seninf;
>>> +
>>> +       /* Set analog phy mode to DPHY */
>>> +       if (is_cdphy_combo(port))
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A, RG_CSI0A_CPHY_EN, 0);
>>> +       /* 4D1C: MIPIRX_ANALOG_A_BASE = 0x00001A42 */
>>> +       if (is_4d1c(port)) {
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
>>> +                           RG_CSI0A_DPHY_L0_CKMODE_EN, 0);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
>>> +                           RG_CSI0A_DPHY_L0_CKSEL, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
>>> +                           RG_CSI0A_DPHY_L1_CKMODE_EN, 0);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
>>> +                           RG_CSI0A_DPHY_L1_CKSEL, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
>>> +                           RG_CSI0A_DPHY_L2_CKMODE_EN, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
>>> +                           RG_CSI0A_DPHY_L2_CKSEL, 1);
>>> +       } else {/* MIPIRX_ANALOG_BASE = 0x102 */
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
>>> +                           RG_CSI0A_DPHY_L0_CKMODE_EN, 0);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
>>> +                           RG_CSI0A_DPHY_L0_CKSEL, 0);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
>>> +                           RG_CSI0A_DPHY_L1_CKMODE_EN, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
>>> +                           RG_CSI0A_DPHY_L1_CKSEL, 0);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
>>> +                           RG_CSI0A_DPHY_L2_CKMODE_EN, 0);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
>>> +                           RG_CSI0A_DPHY_L2_CKSEL, 0);
>>> +       }
>>> +       if (is_cdphy_combo(port))
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
>>> + RG_CSI0B_CPHY_EN, 0);
>>> +
>>> +       /* Only 4d1c need set CSIB: MIPIRX_ANALOG_B_BASE = 0x00001242 */
>>> +       if (is_4d1c(port)) {
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
>>> +                           RG_CSI0B_DPHY_L0_CKMODE_EN, 0);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
>>> +                           RG_CSI0B_DPHY_L0_CKSEL, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
>>> +                           RG_CSI0B_DPHY_L1_CKMODE_EN, 0);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
>>> +                           RG_CSI0B_DPHY_L1_CKSEL, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
>>> +                           RG_CSI0B_DPHY_L2_CKMODE_EN, 0);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
>>> +                           RG_CSI0B_DPHY_L2_CKSEL, 1);
>>> +       } else {/* MIPIRX_ANALOG_BASE = 0x102 */
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
>>> +                           RG_CSI0B_DPHY_L0_CKSEL, 0);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
>>> +                           RG_CSI0B_DPHY_L1_CKMODE_EN, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
>>> +                           RG_CSI0B_DPHY_L1_CKSEL, 0);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
>>> +                           RG_CSI0B_DPHY_L2_CKMODE_EN, 0);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
>>> +                           RG_CSI0B_DPHY_L2_CKSEL, 0);
>>> +       }
>>> +       /* Byte clock invert */
>>> +       SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0A,
>>> +                   RG_CSI0A_CDPHY_L0_T0_BYTECK_INVERT, 1);
>>> +       SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0A,
>>> +                   RG_CSI0A_DPHY_L1_BYTECK_INVERT, 1);
>>> +       SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0A,
>>> +                   RG_CSI0A_CDPHY_L2_T1_BYTECK_INVERT, 1);
>>> +
>>> +       if (is_4d1c(port)) {
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0B,
>>> +                           RG_CSI0B_CDPHY_L0_T0_BYTECK_INVERT, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0B,
>>> +                           RG_CSI0B_DPHY_L1_BYTECK_INVERT, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0B,
>>> +                           RG_CSI0B_CDPHY_L2_T1_BYTECK_INVERT, 1);
>>> +       }
>>> +
>>> +       /* Start ANA EQ tuning */
>>> +       if (is_cdphy_combo(port)) {
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0A,
>>> +                           RG_CSI0A_L0_T0AB_EQ_IS, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0A,
>>> +                           RG_CSI0A_L0_T0AB_EQ_BW, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0A,
>>> +                           RG_CSI0A_L1_T1AB_EQ_IS, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0A,
>>> +                           RG_CSI0A_L1_T1AB_EQ_BW, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0A,
>>> +                           RG_CSI0A_L2_T1BC_EQ_IS, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0A,
>>> +                           RG_CSI0A_L2_T1BC_EQ_BW, 1);
>>> +
>>> +               if (is_4d1c(port)) { /* 4d1c */
>>> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0B,
>>> +                                   RG_CSI0B_L0_T0AB_EQ_IS, 1);
>>> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0B,
>>> +                                   RG_CSI0B_L0_T0AB_EQ_BW, 1);
>>> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0B,
>>> +                                   RG_CSI0B_L1_T1AB_EQ_IS, 1);
>>> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0B,
>>> +                                   RG_CSI0B_L1_T1AB_EQ_BW, 1);
>>> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0B,
>>> +                                   RG_CSI0B_L2_T1BC_EQ_IS, 1);
>>> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0B,
>>> +                                   RG_CSI0B_L2_T1BC_EQ_BW, 1);
>>> +               }
>>> +       } else {
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
>>> +                           RG_CSI1A_L0_EQ_IS, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
>>> +                           RG_CSI1A_L0_EQ_BW, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
>>> +                           RG_CSI1A_L1_EQ_IS, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
>>> +                           RG_CSI1A_L1_EQ_BW, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1A,
>>> +                           RG_CSI1A_L2_EQ_IS, 1);
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1A,
>>> +                           RG_CSI1A_L2_EQ_BW, 1);
>>> +
>>> +               if (is_4d1c(port)) { /* 4d1c */
>>> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
>>> +                                   RG_CSI1B_L0_EQ_IS, 1);
>>> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
>>> +                                   RG_CSI1B_L0_EQ_BW, 1);
>>> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
>>> +                                   RG_CSI1B_L1_EQ_IS, 1);
>>> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
>>> +                                   RG_CSI1B_L1_EQ_BW, 1);
>>> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1B,
>>> +                                   RG_CSI1B_L2_EQ_IS, 1);
>>> +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1B,
>>> +                                   RG_CSI1B_L2_EQ_BW, 1);
>>> +               }
>>> +       }
>>> +
>>> +       /* End ANA EQ tuning */
>>> +       writel(0x90, pmipi_rx_base + MIPI_RX_ANA40_CSI0A);
>>> +       SENINF_BITS(pmipi_rx, MIPI_RX_ANA24_CSI0A,
>>> +                   RG_CSI0A_RESERVE, 0x40);
>>> +       if (is_4d1c(port))
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA24_CSI0B,
>>> +                           RG_CSI0B_RESERVE, 0x40);
>>> +       SENINF_BITS(pmipi_rx, MIPI_RX_WRAPPER80_CSI0A,
>>> +                   CSR_CSI_RST_MODE, 0);
>>> +       if (is_4d1c(port))
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_WRAPPER80_CSI0B,
>>> +                           CSR_CSI_RST_MODE, 0);
>>> +       /* ANA power on */
>>> +       SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
>>> +                   RG_CSI0A_BG_CORE_EN, 1);
>>> +       if (is_4d1c(port))
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
>>> +                           RG_CSI0B_BG_CORE_EN, 1);
>>> +       usleep_range(20, 40);
>>> +       SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
>>> +                   RG_CSI0A_BG_LPF_EN, 1);
>>> +       if (is_4d1c(port))
>>> +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
>>> +                           RG_CSI0B_BG_LPF_EN, 1);
>>> +
>>> +       udelay(1);
>>> +       /* 4d1c: MIPIRX_CONFIG_CSI_BASE = 0xC9000000; */
>>> +       if (is_4d1c(port)) {
>>> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
>>> +                           CSI0_BIST_LN0_MUX, 1);
>>> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
>>> +                           CSI0_BIST_LN1_MUX, 2);
>>> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
>>> +                           CSI0_BIST_LN2_MUX, 0);
>>> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
>>> +                           CSI0_BIST_LN3_MUX, 3);
>>> +       } else { /* 2d1c: MIPIRX_CONFIG_CSI_BASE = 0xE4000000; */
>>> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
>>> +                           CSI0_BIST_LN0_MUX, 0);
>>> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
>>> +                           CSI0_BIST_LN1_MUX, 1);
>>> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
>>> +                           CSI0_BIST_LN2_MUX, 2);
>>> +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
>>> +                           CSI0_BIST_LN3_MUX, 3);
>>> +       }
>>> +}
>>
>> I think the phy control part should be placed in drivers/phy/mediatek/. In [1], device csis point to a device mipi_phy.
>> csis' driver is in [2], and mipi_phy's driver is in [3]
>>
>> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/exynos4.dtsi?h=v5.6
>> [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/media/platform/exynos4-is/mipi-csis.c?h=v5.6
>> [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/phy/samsung/phy-exynos-mipi-video.c?h=v5.6
>>
>> Regards,
>> Chun-Kuang.

Chun-Kuang Hu June 21, 2020, 3:41 p.m. UTC | #5

Hi, Louis:

Louis Kuo (郭德寧) <louis.kuo@mediatek.com> 於 2020年6月21日 週日 下午3:41寫道：
>
> Hi Chun-Kuang,
>
> From phy doc, phy framework is only used to devices that use "external PHY".
>
> But for MTK MT8183, all the modules, include mipi csi dphy(in sensor interface module), image processor, video codec, modem, etc.,
> are embedded in one chip.
>
> Namely, for MT8183, PHY functionality is embedded within controller,
> so I think it's not suitable to regard MTK MTK8183 mipi csi dphy as an independent phy device.
>
> What is your advice?

You think this SoC is only one device which has multiple functions
including csi dphy, image processor, video codec, etc., but I don't
think we should treat this SoC is just one device. In device tree, we
have define many devices in this SoC. We may have a sensor interface
device (the phy controller) and csi dphy device (the phy provider). I
think the register defined in mtk_seninf_rx_reg.h is controlled by csi
dphy device. Is it only about phy? If so, I think phy is independent
and not embedded. If not, please explain what's the other function in
mtk_seninf_rx_reg.h.

Regards,
Chun-Kuang.

>
>  =========================
> |           MT8183  phone SOC             |
> |        =================         |
> |        |        MTK sensor         |     |
> |        |    interface module  |          |
> |        |        Internal PHY        |            |
> |        =================         |
>  =========================
>                       ^   ^   ^    ^
>                       |    |   |    |
>                   ===========
>                  |     sensor       |
>                   ===========
>
> In https://www.kernel.org/doc/Documentation/phy.txt
> This framework will be of use only to devices that use external PHY (PHY
> functionality is not embedded within the controller).
>
>
> BRs
> Louis
>
>
>
>
> -----Original Message-----
> From: Louis Kuo (郭德寧)
> Sent: Monday, April 13, 2020 9:40 PM
> To: Chun-Kuang Hu
> Cc: hans.verkuil@cisco.com; laurent.pinchart+renesas@ideasonboard.com; tfiga@chromium.org; keiichiw@chromium.org; Matthias Brugger; Mauro Carvalho Chehab; devicetree@vger.kernel.org; Sean Cheng (鄭昇弘); srv_heupstream; Jerry-ch Chen (陳敬憲); Jungo Lin (林明俊); Sj Huang (黃信璋); yuzhao@chromium.org; moderated list:ARM/Mediatek SoC support; zwisler@chromium.org; Christie Yu (游雅惠); Frederic Chen (陳俊元); Linux ARM; linux-media@vger.kernel.org
> Subject: RE: [RFC PATCH V6 1/3] media: platform: mtk-isp: Add Mediatek sensor interface driver
>
> Hi Chun-Kuang,
>
> You wrote:
> > I think the phy control part should be placed in drivers/phy/mediatek/. In [1], device csis point to a device mipi_phy.
> > csis' driver is in [2], and mipi_phy's driver is in [3]
> >
> > [1]
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tre
> > e/arch/arm/boot/dts/exynos4.dtsi?h=v5.6
> > [2]
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tre
> > e/drivers/media/platform/exynos4-is/mipi-csis.c?h=v5.6
> > [3]
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tre
> > e/drivers/phy/samsung/phy-exynos-mipi-video.c?h=v5.6
>
> I understood your suggestion to let mipi-csi phy control part as a phy device and use devm_phy_get/phy_configure/phy_power_on/phy_power_off phy API to control it.
>
> I will try to revise it if feasible.
>
> BRs
> Louis
>
>
> -----Original Message-----
> From: Chun-Kuang Hu [mailto:chunkuang.hu@kernel.org]
> Sent: Monday, April 13, 2020 5:27 PM
> To: Louis Kuo (郭德寧) <louis.kuo@mediatek.com>
> Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>; hans.verkuil@cisco.com; laurent.pinchart+renesas@ideasonboard.com; tfiga@chromium.org; keiichiw@chromium.org; Matthias Brugger <matthias.bgg@gmail.com>; Mauro Carvalho Chehab <mchehab@kernel.org>; devicetree@vger.kernel.org; Sean Cheng (鄭昇弘) <Sean.Cheng@mediatek.com>; srv_heupstream <srv_heupstream@mediatek.com>; Jerry-ch Chen (陳敬憲) <Jerry-ch.Chen@mediatek.com>; Jungo Lin (林明俊) <jungo.lin@mediatek.com>; Sj Huang (黃信璋) <sj.huang@mediatek.com>; yuzhao@chromium.org; moderated list:ARM/Mediatek SoC support <linux-mediatek@lists.infradead.org>; zwisler@chromium.org; Christie Yu (游雅惠) <christie.yu@mediatek.com>; Frederic Chen (陳俊元) <Frederic.Chen@mediatek.com>; Linux ARM <linux-arm-kernel@lists.infradead.org>; linux-media@vger.kernel.org
> Subject: Re: [RFC PATCH V6 1/3] media: platform: mtk-isp: Add Mediatek sensor interface driver
>
> Hi, Louis:
>
> Louis Kuo (郭德寧) <louis.kuo@mediatek.com> 於 2020年4月13日 週一 上午10:04寫道：
> >
> > Hi Chun-Kuang,
> >
> > The comment you mentioned,
> > I think the phy control part should be placed in drivers/phy/mediatek/. In [1], device csis point to a device mipi_phy.
> > csis' driver is in [2], and mipi_phy's driver is in [3]
> >
> > I reply as below,
> > =>
> > Since Seninf module includes mipi-csi phy, top mux, mux ctrl parts,
> > combine all together into a v4l2-subdev linking with v4l2 sensor drivers and v4l2 ISP driver backward and forward to transmit and process image.
> >
>
> It  seems that seninf is a mfd or syscon device. MMSYS  [1] is a system controller which control multiple functions. Its major driver is placed in [2], and its clock control function is placed in [3].
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt?h=next-20200413
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/soc/mediatek/mtk-mmsys.c?h=next-20200413
> [3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/clk/mediatek/clk-mt8173-mm.c?h=next-20200413
>
> > The data lanes and port settings is configured by v4l2 sensor drivers,
> > For control reason, it's a better way to let seninf mipi-csi part
> > inside seninf v4l2-subdev rather than an independent phy device in
> > drivers/phy/mediatek
> >
> > There have similar design in omap4iss and Rkisp1-isp driver, they all in staging step.
> > https://elixir.bootlin.com/linux/v5.6/source/drivers/staging/media/rki
> > sp1
> > https://elixir.bootlin.com/linux/v5.6/source/drivers/staging/media/oma
> > p4iss
>
> Staging driver means there are some things need to modify to move out of staging folder, so I think this is not a strong reason to keep phy control in drivers/media/ folder. You could move this driver to drivers/staging/media/ folder and I would have no comment about this.
>
> Regards,
> Chun-Kuang.
>
> >
> > BRs
> > Louis
> >
> > -----Original Message-----
> > From: Chun-Kuang Hu [mailto:chunkuang.hu@kernel.org]
> > Sent: Saturday, April 11, 2020 8:17 AM
> > To: Louis Kuo (郭德寧) <louis.kuo@mediatek.com>
> > Cc: hans.verkuil@cisco.com; laurent.pinchart+renesas@ideasonboard.com;
> > tfiga@chromium.org; keiichiw@chromium.org; Matthias Brugger
> > <matthias.bgg@gmail.com>; Mauro Carvalho Chehab <mchehab@kernel.org>;
> > devicetree@vger.kernel.org; Sean Cheng (鄭昇弘)
> > <Sean.Cheng@mediatek.com>; srv_heupstream
> > <srv_heupstream@mediatek.com>; Jerry-ch Chen (陳敬憲)
> > <Jerry-ch.Chen@mediatek.com>; Jungo Lin (林明俊)
> > <jungo.lin@mediatek.com>; Sj Huang (黃信璋) <sj.huang@mediatek.com>;
> > yuzhao@chromium.org; moderated list:ARM/Mediatek SoC support
> > <linux-mediatek@lists.infradead.org>; zwisler@chromium.org; Christie
> > Yu (游雅惠) <christie.yu@mediatek.com>; Frederic Chen (陳俊元)
> > <Frederic.Chen@mediatek.com>; Linux ARM
> > <linux-arm-kernel@lists.infradead.org>; linux-media@vger.kernel.org
> > Subject: Re: [RFC PATCH V6 1/3] media: platform: mtk-isp: Add Mediatek
> > sensor interface driver
> >
> > Hi, Louis:
> >
> > Louis Kuo <louis.kuo@mediatek.com> 於 2020年4月10日 週五 下午3:18寫道：
> > >
> > > This patch adds Mediatek's sensor interface driver. Sensor interface
> > > driver is a MIPI-CSI2 host driver, namely, a HW camera interface
> > > controller. It support a widely adopted, simple, high-speed protocol
> > > primarily intended for point-to-point image and video transmission
> > > between cameras and host devices. The mtk-isp directory will contain
> > > drivers for multiple IP blocks found in Mediatek ISP system. It will
> > > include ISP Pass 1 driver, sensor interface driver, DIP driver and face detection driver.
> > >
> > > Signed-off-by: Louis Kuo <louis.kuo@mediatek.com>
> > > ---
> > >  drivers/media/platform/Makefile               |    1 +
> > >  drivers/media/platform/mtk-isp/Kconfig        |   18 +
> > >  drivers/media/platform/mtk-isp/Makefile       |    3 +
> > >  .../media/platform/mtk-isp/seninf/Makefile    |    5 +
> > >  drivers/media/platform/mtk-isp/seninf/TODO    |   18 +
> > >  .../platform/mtk-isp/seninf/mtk_seninf.c      | 1173 +++++++++++++
> > >  .../platform/mtk-isp/seninf/mtk_seninf_reg.h  | 1491 +++++++++++++++++
> > >  .../mtk-isp/seninf/mtk_seninf_rx_reg.h        | 1398 ++++++++++++++++
> > >  8 files changed, 4107 insertions(+)  create mode 100644
> > > drivers/media/platform/mtk-isp/Kconfig
> > >  create mode 100644 drivers/media/platform/mtk-isp/Makefile
> > >  create mode 100644 drivers/media/platform/mtk-isp/seninf/Makefile
> > >  create mode 100644 drivers/media/platform/mtk-isp/seninf/TODO
> > >  create mode 100644
> > > drivers/media/platform/mtk-isp/seninf/mtk_seninf.c
> > >  create mode 100644
> > > drivers/media/platform/mtk-isp/seninf/mtk_seninf_reg.h
> > >  create mode 100644
> > > drivers/media/platform/mtk-isp/seninf/mtk_seninf_rx_reg.h
> > >
> >
> > [snip]
> >
> > > +
> > > +static void mtk_seninf_set_dphy(struct mtk_seninf *priv, unsigned
> > > +int
> > > +seninf) {
> > > +       void __iomem *pmipi_rx_base = priv->csi2_rx[CFG_CSI_PORT_0];
> > > +       unsigned int port = priv->port;
> > > +       void __iomem *pmipi_rx = priv->csi2_rx[port];
> > > +       void __iomem *pmipi_rx_conf = priv->base + 0x1000 * seninf;
> > > +
> > > +       /* Set analog phy mode to DPHY */
> > > +       if (is_cdphy_combo(port))
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A, RG_CSI0A_CPHY_EN, 0);
> > > +       /* 4D1C: MIPIRX_ANALOG_A_BASE = 0x00001A42 */
> > > +       if (is_4d1c(port)) {
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > > +                           RG_CSI0A_DPHY_L0_CKMODE_EN, 0);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > > +                           RG_CSI0A_DPHY_L0_CKSEL, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > > +                           RG_CSI0A_DPHY_L1_CKMODE_EN, 0);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > > +                           RG_CSI0A_DPHY_L1_CKSEL, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > > +                           RG_CSI0A_DPHY_L2_CKMODE_EN, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > > +                           RG_CSI0A_DPHY_L2_CKSEL, 1);
> > > +       } else {/* MIPIRX_ANALOG_BASE = 0x102 */
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > > +                           RG_CSI0A_DPHY_L0_CKMODE_EN, 0);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > > +                           RG_CSI0A_DPHY_L0_CKSEL, 0);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > > +                           RG_CSI0A_DPHY_L1_CKMODE_EN, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > > +                           RG_CSI0A_DPHY_L1_CKSEL, 0);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > > +                           RG_CSI0A_DPHY_L2_CKMODE_EN, 0);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > > +                           RG_CSI0A_DPHY_L2_CKSEL, 0);
> > > +       }
> > > +       if (is_cdphy_combo(port))
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > > + RG_CSI0B_CPHY_EN, 0);
> > > +
> > > +       /* Only 4d1c need set CSIB: MIPIRX_ANALOG_B_BASE = 0x00001242 */
> > > +       if (is_4d1c(port)) {
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > > +                           RG_CSI0B_DPHY_L0_CKMODE_EN, 0);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > > +                           RG_CSI0B_DPHY_L0_CKSEL, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > > +                           RG_CSI0B_DPHY_L1_CKMODE_EN, 0);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > > +                           RG_CSI0B_DPHY_L1_CKSEL, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > > +                           RG_CSI0B_DPHY_L2_CKMODE_EN, 0);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > > +                           RG_CSI0B_DPHY_L2_CKSEL, 1);
> > > +       } else {/* MIPIRX_ANALOG_BASE = 0x102 */
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > > +                           RG_CSI0B_DPHY_L0_CKSEL, 0);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > > +                           RG_CSI0B_DPHY_L1_CKMODE_EN, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > > +                           RG_CSI0B_DPHY_L1_CKSEL, 0);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > > +                           RG_CSI0B_DPHY_L2_CKMODE_EN, 0);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > > +                           RG_CSI0B_DPHY_L2_CKSEL, 0);
> > > +       }
> > > +       /* Byte clock invert */
> > > +       SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0A,
> > > +                   RG_CSI0A_CDPHY_L0_T0_BYTECK_INVERT, 1);
> > > +       SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0A,
> > > +                   RG_CSI0A_DPHY_L1_BYTECK_INVERT, 1);
> > > +       SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0A,
> > > +                   RG_CSI0A_CDPHY_L2_T1_BYTECK_INVERT, 1);
> > > +
> > > +       if (is_4d1c(port)) {
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0B,
> > > +                           RG_CSI0B_CDPHY_L0_T0_BYTECK_INVERT, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0B,
> > > +                           RG_CSI0B_DPHY_L1_BYTECK_INVERT, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANAA8_CSI0B,
> > > +                           RG_CSI0B_CDPHY_L2_T1_BYTECK_INVERT, 1);
> > > +       }
> > > +
> > > +       /* Start ANA EQ tuning */
> > > +       if (is_cdphy_combo(port)) {
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0A,
> > > +                           RG_CSI0A_L0_T0AB_EQ_IS, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0A,
> > > +                           RG_CSI0A_L0_T0AB_EQ_BW, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0A,
> > > +                           RG_CSI0A_L1_T1AB_EQ_IS, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0A,
> > > +                           RG_CSI0A_L1_T1AB_EQ_BW, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0A,
> > > +                           RG_CSI0A_L2_T1BC_EQ_IS, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0A,
> > > +                           RG_CSI0A_L2_T1BC_EQ_BW, 1);
> > > +
> > > +               if (is_4d1c(port)) { /* 4d1c */
> > > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0B,
> > > +                                   RG_CSI0B_L0_T0AB_EQ_IS, 1);
> > > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI0B,
> > > +                                   RG_CSI0B_L0_T0AB_EQ_BW, 1);
> > > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0B,
> > > +                                   RG_CSI0B_L1_T1AB_EQ_IS, 1);
> > > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI0B,
> > > +                                   RG_CSI0B_L1_T1AB_EQ_BW, 1);
> > > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0B,
> > > +                                   RG_CSI0B_L2_T1BC_EQ_IS, 1);
> > > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA20_CSI0B,
> > > +                                   RG_CSI0B_L2_T1BC_EQ_BW, 1);
> > > +               }
> > > +       } else {
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
> > > +                           RG_CSI1A_L0_EQ_IS, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
> > > +                           RG_CSI1A_L0_EQ_BW, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
> > > +                           RG_CSI1A_L1_EQ_IS, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1A,
> > > +                           RG_CSI1A_L1_EQ_BW, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1A,
> > > +                           RG_CSI1A_L2_EQ_IS, 1);
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1A,
> > > +                           RG_CSI1A_L2_EQ_BW, 1);
> > > +
> > > +               if (is_4d1c(port)) { /* 4d1c */
> > > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
> > > +                                   RG_CSI1B_L0_EQ_IS, 1);
> > > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
> > > +                                   RG_CSI1B_L0_EQ_BW, 1);
> > > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
> > > +                                   RG_CSI1B_L1_EQ_IS, 1);
> > > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA18_CSI1B,
> > > +                                   RG_CSI1B_L1_EQ_BW, 1);
> > > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1B,
> > > +                                   RG_CSI1B_L2_EQ_IS, 1);
> > > +                       SENINF_BITS(pmipi_rx, MIPI_RX_ANA1C_CSI1B,
> > > +                                   RG_CSI1B_L2_EQ_BW, 1);
> > > +               }
> > > +       }
> > > +
> > > +       /* End ANA EQ tuning */
> > > +       writel(0x90, pmipi_rx_base + MIPI_RX_ANA40_CSI0A);
> > > +       SENINF_BITS(pmipi_rx, MIPI_RX_ANA24_CSI0A,
> > > +                   RG_CSI0A_RESERVE, 0x40);
> > > +       if (is_4d1c(port))
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA24_CSI0B,
> > > +                           RG_CSI0B_RESERVE, 0x40);
> > > +       SENINF_BITS(pmipi_rx, MIPI_RX_WRAPPER80_CSI0A,
> > > +                   CSR_CSI_RST_MODE, 0);
> > > +       if (is_4d1c(port))
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_WRAPPER80_CSI0B,
> > > +                           CSR_CSI_RST_MODE, 0);
> > > +       /* ANA power on */
> > > +       SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > > +                   RG_CSI0A_BG_CORE_EN, 1);
> > > +       if (is_4d1c(port))
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > > +                           RG_CSI0B_BG_CORE_EN, 1);
> > > +       usleep_range(20, 40);
> > > +       SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0A,
> > > +                   RG_CSI0A_BG_LPF_EN, 1);
> > > +       if (is_4d1c(port))
> > > +               SENINF_BITS(pmipi_rx, MIPI_RX_ANA00_CSI0B,
> > > +                           RG_CSI0B_BG_LPF_EN, 1);
> > > +
> > > +       udelay(1);
> > > +       /* 4d1c: MIPIRX_CONFIG_CSI_BASE = 0xC9000000; */
> > > +       if (is_4d1c(port)) {
> > > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > > +                           CSI0_BIST_LN0_MUX, 1);
> > > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > > +                           CSI0_BIST_LN1_MUX, 2);
> > > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > > +                           CSI0_BIST_LN2_MUX, 0);
> > > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > > +                           CSI0_BIST_LN3_MUX, 3);
> > > +       } else { /* 2d1c: MIPIRX_CONFIG_CSI_BASE = 0xE4000000; */
> > > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > > +                           CSI0_BIST_LN0_MUX, 0);
> > > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > > +                           CSI0_BIST_LN1_MUX, 1);
> > > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > > +                           CSI0_BIST_LN2_MUX, 2);
> > > +               SENINF_BITS(pmipi_rx_conf, MIPI_RX_CON24_CSI0,
> > > +                           CSI0_BIST_LN3_MUX, 3);
> > > +       }
> > > +}
> >
> > I think the phy control part should be placed in drivers/phy/mediatek/. In [1], device csis point to a device mipi_phy.
> > csis' driver is in [2], and mipi_phy's driver is in [3]
> >
> > [1]
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tre
> > e/arch/arm/boot/dts/exynos4.dtsi?h=v5.6
> > [2]
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tre
> > e/drivers/media/platform/exynos4-is/mipi-csis.c?h=v5.6
> > [3]
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tre
> > e/drivers/phy/samsung/phy-exynos-mipi-video.c?h=v5.6
> >
> > Regards,
> > Chun-Kuang.

[RFC,V6,0/3] media: support Mediatek sensor interface driver

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