From patchwork Wed Aug 19 13:34:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Elisei X-Patchwork-Id: 11724181 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 467D414E3 for ; Wed, 19 Aug 2020 13:35:39 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 160FA204EC for ; Wed, 19 Aug 2020 13:35:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="3i5xKVuK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 160FA204EC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=Gc8tHcdlbNN59s1HSYnzyHxk+eewUiF9FWpM7n/6NfA=; b=3i5xKVuKicKMwMyok1OOj4RwMe g/5M1JUReoLsx1a1xkCVuZ7yNvz5gJo40j3FKgAn2HsnOFlXHelDqxhWL0poRCuu6XI6vc0w8/H5R QEavKoH2eaz/IkUjyYnB5vlgVguw59UDAUFYpO93nwoZGfHXS6HvWPghiP2vvdvoHQvtG4r2lfwAa FlDrHr6pQqQejH8HAdWh0VpnrDTuZ2oBPVeHIpoRVv72eMToBtU1Y8QtQTrVflLbo3v43fKaQRDHW RObBhlUYknBMKIoPMx/0xZY62tT1k25r4hxjQq5UYtMBwuVXo8bvoQO2HM0jkStDwvektAKdxzGBl vu7QqnoQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k8ODe-0000Jq-1h; Wed, 19 Aug 2020 13:33:34 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k8ODa-0000E1-3G for linux-arm-kernel@lists.infradead.org; Wed, 19 Aug 2020 13:33:31 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3B6421FB; Wed, 19 Aug 2020 06:33:28 -0700 (PDT) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1710E3F71F; Wed, 19 Aug 2020 06:33:26 -0700 (PDT) From: Alexandru Elisei To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 0/7] arm_pmu: Use NMI for perf interrupt Date: Wed, 19 Aug 2020 14:34:12 +0100 Message-Id: <20200819133419.526889-1-alexandru.elisei@arm.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200819_093330_258631_11856234 X-CRM114-Status: GOOD ( 21.57 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, sumit.garg@linaro.org, maz@kernel.org, swboyd@chromium.org, catalin.marinas@arm.com, will@kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The series makes the arm_pmu driver use NMIs for the perf interrupt when NMIs are available on the platform (currently, only arm64 + GICv3). To make it easier to play with the patches, I've pushed a branch at [1]: $ git clone -b pmu-nmi-v6 git://linux-arm.org/linux-ae I've tested the series on an espressobin v7*. These are the results of running perf record -a -- sleep 60: 1. Without the patches: 16.73% [k] arch_local_irq_enable 12.20% [k] arch_cpu_idle 8.61% [k] _raw_spin_unlock_irqrestore 4.09% [k] arch_local_irq_enable 2.25% [k] arch_local_irq_enable 1.82% [k] arch_counter_get_cntpct [..] 2. Using NMIs: 3.37% [k] arch_counter_get_cntpct 2.62% [.] _IO_fwrite 1.62% [.] __gconv_transform_ascii_internal 1.49% [.] __mbrtowc 1.44% [k] el0_svc_common 1.31% [.] strchr [..] When running perf record -a -- iperf3 -c 127.0.0.1 -t 60: 1. Without the patches: 24.25% [k] __arch_copy_from_user 20.94% [k] __arch_copy_to_user 5.71% [k] arch_local_irq_enable 3.12% [k] _raw_spin_unlock_irqrestore 2.01% [k] __free_pages_ok 1.48% [k] arch_cpu_idle [..] 2. Using NMIs: 23.15% [k] __arch_copy_from_user 21.68% [k] __arch_copy_to_user 1.23% [k] tcp_ack 1.08% [k] tcp_sendmsg_locked 0.97% [k] rmqueue 0.91% [k] __free_pages_ok [..] I've ran the same tests in a VM when both host+guest use NMIs, and when neither use them. All of these tests were also ran on the model. Similar results in all cases. * All the firmware versions for espressobin v7 that I've tried clear SCR_EL3.FIQ, which means that NMIs don't work. To make them work on the board, I modified the GICv3 driver. That's why I would really appreciate someone testing this series on a board where NMIs work without any GIC changes. For people who want to test the series, but don't have a board with firmware that sets SCR_EL3.FIQ, I've pushed a branch [2] with the GICv3 drivers changes necessary to make NMIs work: $ git clone -b pmu-nmi-v6-nmi-fiq-clear-v2 git://linux-arm.org/linux-ae Summary of the patches: * Patch 1 is a fix for a bug that Julien found during the review for v4. * Patches 2 and 3 remove locking from arm64 perf event code. * Patches 4 and 5 makes the arm64 PMU interrupt handler NMI safe. * Patches 6 and 7 enable the use of NMIs on arm64 with a GICv3 irqchip. Changes since v5 [3]: - Rebased on top of v5.9-rc1. - Typo fixes. - Added comments to the ISB added by patches #1 and #2. - Reworded message for patch #4, as per Mark's excellent suggestion. Changes since v4 [4]: - Rebased on top of v5.8-rc1 and dropped the Tested-by tags because it's been almost a year since the series has been tested. - Dropped patch 3 because I couldn't find any instance where armv7pmu_read_counter() was called with interrupts enabled. I've also tested this by running several instances of perf for a few hours, and the function was called every time with interrupts disabled. - Dropped patches 4 and 5 because the tradeoff wasn't worth it in my opinion: the irq handler was slower all the time (because it saved/restored the counter select register), in exchange for being slightly faster on the rare ocassions when it triggered at the beginning of the critical sections. - Minor changes here and there to address review comments. Changes since v3 [5]: - Added tags - Fix build issue for perf_event_v6 - Don't disable preemption in pmu->enable() - Always rely on IPI_IRQ_WORK to run the queued work - Fixed typos + cleanups Changes since v2 [6]: - Rebased on recent linux-next (next-20190708) - Fixed a number of bugs with indices (reported by Wei) - Minor style fixes Changes since v1 [7]: - Rebased on v5.1-rc1 - Pseudo-NMI has changed a lot since then, use the (now merged) NMI API - Remove locking from armv7 perf_event - Use locking only in armv6 perf_event - Use direct counter/type registers insted of selector register for armv8 [1] http://www.linux-arm.org/git?p=linux-ae.git;a=shortlog;h=refs/heads/pmu-nmi-v6 [2] http://www.linux-arm.org/git?p=linux-ae.git;a=shortlog;h=refs/heads/pmu-nmi-v6-nmi-fiq-clear-v2 [3] https://www.spinics.net/lists/kernel/msg3554236.html [4] https://lists.infradead.org/pipermail/linux-arm-kernel/2019-July/666824.html [5] https://lists.infradead.org/pipermail/linux-arm-kernel/2019-July/665339.html [6] https://lists.infradead.org/pipermail/linux-arm-kernel/2019-March/640536.html [7] https://lists.infradead.org/pipermail/linux-arm-kernel/2018-January/554611.html Alexandru Elisei (1): arm64: perf: Add missing ISB in armv8pmu_enable_event() Julien Thierry (5): arm64: perf: Remove PMU locking arm64: perf: Defer irq_work to IPI_IRQ_WORK KVM: arm64: pmu: Make overflow handler NMI safe arm_pmu: Introduce pmu_irq_ops arm_pmu: arm64: Use NMIs for PMU Mark Rutland (1): arm64: perf: Avoid PMXEV* indirection arch/arm64/kernel/perf_event.c | 145 +++++++++++++++++++++------------ arch/arm64/kvm/pmu-emul.c | 25 +++++- drivers/perf/arm_pmu.c | 142 +++++++++++++++++++++++++++----- include/kvm/arm_pmu.h | 1 + 4 files changed, 241 insertions(+), 72 deletions(-) Tested-by: Sumit Garg (Developerbox)