From patchwork Wed Aug 26 13:03:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ionela Voinescu X-Patchwork-Id: 11738343 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F124113B1 for ; Wed, 26 Aug 2020 13:04:11 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C6B3720707 for ; Wed, 26 Aug 2020 13:04:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="CqlYdogM" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C6B3720707 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Owner; bh=uqF2MfBifTENjZfhOkBz/gxlBMPzIkwHtmsGimjSHw8=; b=CqlYdogMl2obHReAOSC6F6hs3l exm4WsxSiQuJFz+fYfgCkpVWflzZ8TwpPXLtWTRzfOkgS0y7RUVNlDxB1GkhnPQGy5w3QvOkC2fre h263PIcRX++5kzNntqgUVEoENkIKKGpzf//D7MCO2WgixQOcOKhvU605hbXyLtnMaSUKwEb7iILgN JWgqKZvhtC3a1xplWIpV/KIUNStIX5FyiwltcBGiQ7G87befft7dHV/iW3Jip1WbBN8f8dwrSVH/z 4S6poPFrsPpp8BhFNdjXW5IWkhF9FinKPA4CZYhANhxKWVYoRyIsC8vV6pgfQ03qmM7pbIMrYNh4C eJuqFWOQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kAv5s-0001Tl-Dt; Wed, 26 Aug 2020 13:04:00 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kAv5q-0001Ss-2o for linux-arm-kernel@lists.infradead.org; Wed, 26 Aug 2020 13:03:59 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F0CFE101E; Wed, 26 Aug 2020 06:03:53 -0700 (PDT) Received: from e108754-lin.cambridge.arm.com (unknown [10.1.199.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 838463F68F; Wed, 26 Aug 2020 06:03:52 -0700 (PDT) From: Ionela Voinescu To: catalin.marinas@arm.com, will@kernel.org, sudeep.holla@arm.com Subject: [PATCH 0/4] arm64: cppc: add FFH support using AMUs Date: Wed, 26 Aug 2020 14:03:05 +0100 Message-Id: <20200826130309.28027-1-ionela.voinescu@arm.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200826_090358_226261_8499244C X-CRM114-Status: GOOD ( 10.54 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: souvik.chakravarty@arm.com, viresh.kumar@linaro.org, valentin.schneider@arm.com, linux-kernel@vger.kernel.org, dietmar.eggemann@arm.com, ionela.voinescu@arm.com, morten.rasmussen@arm.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Hi guys, This series adds support for CPPC's delivered and reference performance counters through the FFH methods by using the AMU equivalent core and constant cycle counters. This support is added in patch 4/4, while the first 3 patches generalise the existing AMU counter read and validation functionality to be reused for this usecase. The specification that drove this implementation can be found at [1], chapter 3.2. The code was tested on a Armv8-A Base Platform FVP: Architecture Envelope Model [2] with the following _CPC entry for all CPUs: Name(_CPC, Package() { 23, // NumEntries 3, // Revision 100, // Highest Performance - Fixed 100MHz 100, // Nominal Performance - Fixed 100MHz 1, // Lowest Nonlinear Performance 1, // Lowest Performance ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Guaranteed Performance Register ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Desired Perf Register ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Red. Tolerance Register ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time ResourceTemplate(){Register(FFixedHW, 0x40, 0, 1, 0x4)}, // Reference Performance Counter Register ResourceTemplate(){Register(FFixedHW, 0x40, 0, 0, 0x4)}, // Delivered Performance Counter Register ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Ltd Register ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // CPPC Enable Register ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register 100, // Reference Performance - Fixed 100MHz 1, // Lowest Frequency 100, // Nominal Frequency - Fixed 100MHz }) The following configuration is necessary for Activity Monitors use: cluster0.has_arm_v8-4=1 cluster1.has_arm_v8-4=1 cluster0.has_amu=1 cluster1.has_amu=1 To be noted: - The FVP has fixed core and constant frequency of 100MHz - The kernel I used for testing had some extra debug information as you can see below: $ cat /sys/devices/system/cpu/cpufreq/policy*/cpuinfo_cur_freq [ 23.850590] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (2402*100)/2402=100. 100000 [ 23.851246] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (2402*100)/2402=100. 100000 [ 23.851826] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (2873*100)/2872=100. 100000 [ 23.852326] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (2402*100)/2402=100. 100000 [ 23.852747] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (2309*100)/2309=100. 100000 [ 23.853228] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (1333*100)/1333=100. 100000 [ 23.854097] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (18762*100)/20003=93. 93000 [ 23.854890] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (20047*100)/20051=99. 99000 [1] https://documentation-service.arm.com/static/5f106ad60daa596235e80081 [2] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms Thanks, Ionela. Ionela Voinescu (4): arm64: cpufeature: restructure AMU feedback function arm64: wrap and generalise counter read functions arm64: split counter validation function arm64: implement CPPC FFH support using AMUs arch/arm64/include/asm/cpufeature.h | 6 +- arch/arm64/kernel/cpufeature.c | 15 ++- arch/arm64/kernel/topology.c | 147 ++++++++++++++++++++++------ 3 files changed, 129 insertions(+), 39 deletions(-) base-commit: 3a00d3dfd4b68b208ecd5405e676d06c8ad6bb63