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Tue, 1 Sep 2020 09:06:43 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 1 Sep 2020 09:06:42 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 1 Sep 2020 09:06:42 -0500 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 081E6Zlf034944; Tue, 1 Sep 2020 09:06:36 -0500 From: Kishon Vijay Abraham I To: Tero Kristo , Nishanth Menon , Rob Herring Subject: [RESEND PATCH 0/2] Add DT to get PCIe working in J721E SoC Date: Tue, 1 Sep 2020 19:36:26 +0530 Message-ID: <20200901140628.8800-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200901_100646_024966_CBF13C49 X-CRM114-Status: GOOD ( 10.47 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [198.47.19.141 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kishon Vijay Abraham I Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Now that J721E PCIe support is merged (including the YAML bindings), add PCIe device tree nodes to get PCIe working in J721E SoC both in RC mode and EP mode. Series has been rebased to: git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux ti-k3-dts-next No changes from the previous version sent to http://lore.kernel.org/r/20200724055604.31498-1-kishon@ti.com Kishon Vijay Abraham I (2): arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances .../dts/ti/k3-j721e-common-proc-board.dts | 80 +++++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +- 3 files changed, 302 insertions(+), 1 deletion(-)