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d="scan'208";a="153530914" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 06 Oct 2020 08:17:56 +0800 IronPort-SDR: ia2r14+IUZfZHV8owtXSibtteW/lyCVdAtsG9QHiceq7n/CUBW8RFEZ1jJ59M5whWPzOduYPzF b2Plr1gxR5fA== Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Oct 2020 17:04:42 -0700 IronPort-SDR: Neg4gQXFt16GausLnkBfK7NTrO7uOhLbWHdiEHDf+HDtgOth4FjfITodd3H2Qum9/EAwzsM5gp ULdHQ5pTY/EA== WDCIronportException: Internal Received: from b9f8262.ad.shared (HELO jedi-01.hgst.com) ([10.86.59.253]) by uls-op-cesaip01.wdc.com with ESMTP; 05 Oct 2020 17:17:55 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH v4 0/5] Unify NUMA implementation between ARM64 & RISC-V Date: Mon, 5 Oct 2020 17:17:47 -0700 Message-Id: <20201006001752.248564-1-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201005_201803_786110_5457CB23 X-CRM114-Status: GOOD ( 21.51 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [216.71.153.141 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kefeng Wang , David Hildenbrand , Catalin Marinas , Jonathan Cameron , Atish Patra , Zong Li , linux-riscv@lists.infradead.org, Will Deacon , linux-arch@vger.kernel.org, Jia He , Anup Patel , "Rafael J. Wysocki" , Steven Price , Greentime Hu , Albert Ou , Arnd Bergmann , Anshuman Khandual , Paul Walmsley , linux-arm-kernel@lists.infradead.org, Greg Kroah-Hartman , Palmer Dabbelt , Mike Rapoport , Andrew Morton , Nicolas Saenz Julienne Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This series attempts to move the ARM64 numa implementation to common code so that RISC-V can leverage that as well instead of reimplementing it again. RISC-V specific bits are based on initial work done by Greentime Hu [1] but modified to reuse the common implementation to avoid duplication. [1] https://lkml.org/lkml/2020/1/10/233 This series has been tested on qemu with numa enabled for both RISC-V & ARM64. It would be great if somebody can test it on numa capable ARM64 hardware platforms. This patch series doesn't modify the maintainers list for the common code (arch_numa) as I am not sure if somebody from ARM64 community or Greg should take up the maintainership. Ganapatrao was the original author of the arm64 version. I would be happy to update that in the next revision once it is decided. # numactl --hardware available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 node 0 size: 486 MB node 0 free: 470 MB node 1 cpus: 4 5 6 7 node 1 size: 424 MB node 1 free: 408 MB node distances: node 0 1 0: 10 20 1: 20 10 # numactl -show policy: default preferred node: current physcpubind: 0 1 2 3 4 5 6 7 cpubind: 0 1 nodebind: 0 1 membind: 0 1 The patches are also available at https://github.com/atishp04/linux/tree/5.10_numa_unified_v4 For RISC-V, the following qemu series is a pre-requisite(already available in upstream) https://patchwork.kernel.org/project/qemu-devel/list/?series=303313 Testing: RISC-V: Tested in Qemu and 2 socket OmniXtend FPGA. ARM64: 2 socket kunpeng920 (4 nodes around 250G a node) Tested-by: Jonathan Cameron There may be some minor conflicts with Mike's cleanup series [2] depending on the order in which these two series are being accepted. I can rebase on top his series if required. [2] https://lkml.org/lkml/2020/8/18/754 Changes from v3->v4: 1. Removed redundant duplicate header. 2. Added Reviewed-by tags. Changes from v2->v3: 1. Added Acked-by/Reviewed-by tags. 2. Replaced asm/acpi.h with linux/acpi.h 3. Defined arch_acpi_numa_init as static. Changes from v1->v2: 1. Replaced ARM64 specific compile time protection with ACPI specific ones. 2. Dropped common pcibus_to_node changes. Added required changes in RISC-V. 3. Fixed few typos. Atish Patra (4): numa: Move numa implementation to common code arm64, numa: Change the numa init functions name to be generic riscv: Separate memory init from paging init riscv: Add numa support for riscv64 platform Greentime Hu (1): riscv: Add support pte_protnone and pmd_protnone if CONFIG_NUMA_BALANCING arch/arm64/Kconfig | 1 + arch/arm64/include/asm/numa.h | 45 +---------------- arch/arm64/kernel/acpi_numa.c | 13 ----- arch/arm64/mm/Makefile | 1 - arch/arm64/mm/init.c | 4 +- arch/riscv/Kconfig | 31 +++++++++++- arch/riscv/include/asm/mmzone.h | 13 +++++ arch/riscv/include/asm/numa.h | 8 +++ arch/riscv/include/asm/pci.h | 14 ++++++ arch/riscv/include/asm/pgtable.h | 21 ++++++++ arch/riscv/kernel/setup.c | 11 ++++- arch/riscv/kernel/smpboot.c | 12 ++++- arch/riscv/mm/init.c | 10 +++- drivers/base/Kconfig | 6 +++ drivers/base/Makefile | 1 + .../mm/numa.c => drivers/base/arch_numa.c | 30 ++++++++++-- include/asm-generic/numa.h | 49 +++++++++++++++++++ 17 files changed, 199 insertions(+), 71 deletions(-) create mode 100644 arch/riscv/include/asm/mmzone.h create mode 100644 arch/riscv/include/asm/numa.h rename arch/arm64/mm/numa.c => drivers/base/arch_numa.c (95%) create mode 100644 include/asm-generic/numa.h --- 2.25.1