mbox series

[v4,0/3] arm64: cppc: add FFH support using AMUs

Message ID 20201106125334.21570-1-ionela.voinescu@arm.com (mailing list archive)
Headers show
Series arm64: cppc: add FFH support using AMUs | expand

Message

Ionela Voinescu Nov. 6, 2020, 12:53 p.m. UTC 
Hi guys,

Many thanks for everyone's review.

This series adds support for CPPC's delivered and reference performance
counters through the FFH methods by using the AMU equivalent core and
constant cycle counters.

This support is added in patch 3/3, while the first 2 patches generalise
the existing AMU counter read and validation functionality to be reused
for this usecase.

The specification that drove this implementation can be found at [1],
chapter 3.2.

v3 -> v4:
 - v3 can be found at [4]
 - 1/3, 3/3: Modified counter read functions as per Mark's suggestions.
 - This version is based on v5.10-rc2

v2 -> v3:
 - v2 can be found at [3]
 - Sorted out part of the issues flagged by 0day testing in patches 1/3
   and 3/3.
 - This version is based on v5.10-rc2.

RESEND v2:
 - Rebased and retested on v5.10-rc1.

v1 -> v2:
 - v1 can be found at [2]
 - The previous patch 1/4 was removed and a get_cpu_with_amu_feat()
   function was introduced instead, in 3/3, as suggested by Catalin.
   Given that most checks for the presence of AMUs is done at CPU
   level, followed by other validation, this implementation works
   better than the one initially introduced in v1/->patch 1/4.
 - Fixed warning reported by 0-day kernel test robot.
 - All build tests and FVP tests at [2] were re-run for this version.
 - This version is based on linux-next/20201001.

[1] https://documentation-service.arm.com/static/5f106ad60daa596235e80081
[2] https://lore.kernel.org/lkml/20200826130309.28027-1-ionela.voinescu@arm.com/
[3] https://lore.kernel.org/linux-arm-kernel/20201027163624.20747-1-ionela.voinescu@arm.com/
[4] https://lore.kernel.org/linux-arm-kernel/20201105122702.13916-1-ionela.voinescu@arm.com/

Thank you,
Ionela.

Ionela Voinescu (3):
  arm64: wrap and generalise counter read functions
  arm64: split counter validation function
  arm64: implement CPPC FFH support using AMUs

 arch/arm64/include/asm/cpufeature.h |   8 ++
 arch/arm64/include/asm/topology.h   |   4 +-
 arch/arm64/kernel/cpufeature.c      |  13 ++-
 arch/arm64/kernel/topology.c        | 129 ++++++++++++++++++++++------
 4 files changed, 124 insertions(+), 30 deletions(-)

Comments

Catalin Marinas Nov. 13, 2020, 8:26 p.m. UTC | #1 
On Fri, 6 Nov 2020 12:53:31 +0000, Ionela Voinescu wrote:
> Many thanks for everyone's review.
> 
> This series adds support for CPPC's delivered and reference performance
> counters through the FFH methods by using the AMU equivalent core and
> constant cycle counters.
> 
> This support is added in patch 3/3, while the first 2 patches generalise
> the existing AMU counter read and validation functionality to be reused
> for this usecase.
> 
> [...]

Applied to arm64 (for-next/cppc-ffh), thanks!

[1/3] arm64: wrap and generalise counter read functions
      https://git.kernel.org/arm64/c/4b9cf23c179a
[2/3] arm64: split counter validation function
      https://git.kernel.org/arm64/c/bc3b6562a1ac
[3/3] arm64: implement CPPC FFH support using AMUs
      https://git.kernel.org/arm64/c/68c5debcc06d

I also applied the irq_disabled() abort as per Mark's comments:

      https://git.kernel.org/arm64/c/74490422522d