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Tue, 05 Jan 2021 10:05:34 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 44094100034; Tue, 5 Jan 2021 10:05:33 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2D52322AA5B; Tue, 5 Jan 2021 10:05:33 +0100 (CET) Received: from localhost (10.75.127.44) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 5 Jan 2021 10:05:32 +0100 From: Amelie Delaunay To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Alexandre Torgue , Maxime Coquelin Subject: [PATCH v2 0/6] STM32 USBPHYC PLL management rework Date: Tue, 5 Jan 2021 10:05:19 +0100 Message-ID: <20210105090525.23164-1-amelie.delaunay@foss.st.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG3NODE3.st.com (10.75.127.9) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-05_01:2021-01-05, 2021-01-05 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210105_040541_926242_E1E51D8D X-CRM114-Status: GOOD ( 12.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amelie Delaunay , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org STM32 USBPHYC controls the USB PLL. PLL requires to be powered with 1v1 and 1v8 supplies. To ensure a good behavior of the PLL, during boot, runtime and suspend/resume sequences, this series reworks its management to fix regulators issues and improve PLL status reliability. --- Changes in v2: - Move author mail address from @st.com to @foss.st.com - Add Rob's Reviewed-by on bindings patch 1/6 Amelie Delaunay (6): dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation phy: stm32: replace regulator_bulk* by multiple regulator_* phy: stm32: ensure pll is disabled before phys creation phy: stm32: ensure phy are no more active when removing the driver phy: stm32: rework PLL Lock detection .../bindings/phy/phy-stm32-usbphyc.yaml | 22 +- drivers/phy/st/phy-stm32-usbphyc.c | 222 +++++++++++------- 2 files changed, 153 insertions(+), 91 deletions(-)