[v3,0/3] Add Hisilicon L3 cache controller support

Message

Leizhen (ThunderTown) Jan. 12, 2021, 1:55 a.m. UTC

v2 --> v3:
Add Hisilicon L3 cache controller driver and its document. That's: patch 2-3.

v1 --> v2:
Discard the middle-tier functions and do silent narrowing cast in the outcache
hook functions. For example:
-static void l2c220_inv_range(unsigned long start, unsigned long end)
+static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
 {
+	unsigned long start = pa_start;
+	unsigned long end = pa_end;


v1:
Do cast phys_addr_t to unsigned long by adding a middle-tier function.
For example:
-static void l2c220_inv_range(unsigned long start, unsigned long end)
+static void __l2c220_inv_range(unsigned long start, unsigned long end)
 {
 	...
 }
+static void l2c220_inv_range(phys_addr_t start, phys_addr_t end)
+{
+  __l2c220_inv_range(start, end);
+}


Zhen Lei (3):
  ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache
    hooks
  dt-bindings: arm: hisilicon: Add binding for L3 cache controller
  ARM: Add Hisilicon L3 cache controller support

 .../bindings/arm/hisilicon/l3cache.yaml       |  37 +++++
 arch/arm/include/asm/outercache.h             |   6 +-
 arch/arm/mm/Kconfig                           |   9 ++
 arch/arm/mm/Makefile                          |   1 +
 arch/arm/mm/cache-feroceon-l2.c               |  15 +-
 arch/arm/mm/cache-hisi-l3.c                   | 153 ++++++++++++++++++
 arch/arm/mm/cache-hisi-l3.h                   |  30 ++++
 arch/arm/mm/cache-l2x0.c                      |  50 ++++--
 arch/arm/mm/cache-tauros2.c                   |  15 +-
 arch/arm/mm/cache-uniphier.c                  |   6 +-
 arch/arm/mm/cache-xsc3l2.c                    |  12 +-
 11 files changed, 305 insertions(+), 29 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml
 create mode 100644 arch/arm/mm/cache-hisi-l3.c
 create mode 100644 arch/arm/mm/cache-hisi-l3.h