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dmarc=none action=none header.from=nxp.com; Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) by HE1PR04MB3276.eurprd04.prod.outlook.com (2603:10a6:7:22::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3999.32; Wed, 7 Apr 2021 03:03:32 +0000 Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::5df8:1a69:47c3:44fc]) by HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::5df8:1a69:47c3:44fc%3]) with mapi id 15.20.3999.032; Wed, 7 Apr 2021 03:03:32 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, Hou Zhiqiang Subject: [PATCHv5 0/6] PCI: layerscape: Add power management support Date: Wed, 7 Apr 2021 11:09:42 +0800 Message-Id: <20210407030948.3845-1-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 X-Originating-IP: [119.31.174.73] X-ClientProxiedBy: MA1PR01CA0156.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::26) To HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.73) by MA1PR01CA0156.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4020.17 via Frontend Transport; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Hou Zhiqiang This patch series is to add PCIe power management support for NXP Layerscape platforms. Hou Zhiqiang (6): PCI: layerscape: Change to use the DWC common link-up check function dt-bindings: pci: layerscape-pci: Add a optional property big-endian arm64: dts: layerscape: Add big-endian property for PCIe nodes dt-bindings: pci: layerscape-pci: Update the description of SCFG property arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes PCI: layerscape: Add power management support .../bindings/pci/layerscape-pci.txt | 6 +- .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 + .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 + .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 + drivers/pci/controller/dwc/pci-layerscape.c | 450 ++++++++++++++---- drivers/pci/controller/dwc/pcie-designware.h | 1 + 6 files changed, 370 insertions(+), 97 deletions(-)