| Message ID | 20210430052746.10815-1-peng.fan@oss.nxp.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | soc: imx: add i.MX BLK-CTL support | expand |
> Subject: [PATCH V2 0/4] soc: imx: add i.MX BLK-CTL support > > From: Peng Fan <peng.fan@nxp.com> > > V2: > Fix yaml check failure Forget the address Jacky's comments on patch 3,4 in V1. Will send V3 to add fix. Thanks, Peng. > > Previously there is an effort from Abel that take BLK-CTL as clock provider, but > it turns out that there is A/B lock issue and we are not able resolve that. > > Per discuss with Lucas and Jacky, we made an agreement that take BLK-CTL > as a power domain provider and use GPC's domain as parent, the consumer > node take BLK-CTL as power domain input. > > This patchset has been tested on i.MX8MM EVK board, but one hack is not > included in the patchset is that the DISPMIX BLK-CTL MIPI_M/S_RESET not > implemented. Per Lucas, we will finally have a MIPI DPHY driver, so fine to > leave it. > > Thanks for Lucas's suggestion, Frieder Schrempf for collecting all the patches, > Abel's previous BLK-CTL work, Jacky Bai on help debug issues. > > Peng Fan (4): > dt-bindings: power: Add defines for i.MX8MM BLK-CTL power domains > Documentation: bindings: clk: Add bindings for i.MX BLK_CTL > soc: imx: Add generic blk-ctl driver > soc: imx: Add blk-ctl driver for i.MX8MM > > .../bindings/soc/imx/fsl,imx-blk-ctl.yaml | 73 +++++ > drivers/soc/imx/Makefile | 2 +- > drivers/soc/imx/blk-ctl-imx8mm.c | 138 ++++++++ > drivers/soc/imx/blk-ctl.c | 303 > ++++++++++++++++++ > drivers/soc/imx/blk-ctl.h | 76 +++++ > include/dt-bindings/power/imx8mm-power.h | 11 + > 6 files changed, 602 insertions(+), 1 deletion(-) create mode 100644 > Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml > create mode 100644 drivers/soc/imx/blk-ctl-imx8mm.c create mode > 100644 drivers/soc/imx/blk-ctl.c create mode 100644 > drivers/soc/imx/blk-ctl.h > > -- > 2.30.0
Hi Peng, On 30.04.21 07:27, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > V2: > Fix yaml check failure > > Previously there is an effort from Abel that take BLK-CTL as clock > provider, but it turns out that there is A/B lock issue and we are > not able resolve that. > > Per discuss with Lucas and Jacky, we made an agreement that take BLK-CTL > as a power domain provider and use GPC's domain as parent, the consumer > node take BLK-CTL as power domain input. > > This patchset has been tested on i.MX8MM EVK board, but one hack > is not included in the patchset is that the DISPMIX BLK-CTL MIPI_M/S_RESET > not implemented. Per Lucas, we will finally have a MIPI DPHY driver, > so fine to leave it. Thanks for your work. I would like to test this together with the DSIM and PHY driver by Michael and Marek. So far the boot hangs when probing the DSIM, but I'm not even sure if my DT is correct. With the DSIM PHY driver (see [1]) in place, the GPR_MIPI_M_RESETN should be set correctly, right? Would you mind sharing your imx8mm.dtsi, that you used for testing? Thanks Frieder [1] https://patchwork.kernel.org/project/linux-samsung-soc/patch/20201003225020.164358-1-marex@denx.de/
On 03.05.21 16:57, Frieder Schrempf wrote: > Hi Peng, > > On 30.04.21 07:27, Peng Fan (OSS) wrote: >> From: Peng Fan <peng.fan@nxp.com> >> >> V2: >> Fix yaml check failure >> >> Previously there is an effort from Abel that take BLK-CTL as clock >> provider, but it turns out that there is A/B lock issue and we are >> not able resolve that. >> >> Per discuss with Lucas and Jacky, we made an agreement that take BLK-CTL >> as a power domain provider and use GPC's domain as parent, the consumer >> node take BLK-CTL as power domain input. >> >> This patchset has been tested on i.MX8MM EVK board, but one hack >> is not included in the patchset is that the DISPMIX BLK-CTL >> MIPI_M/S_RESET >> not implemented. Per Lucas, we will finally have a MIPI DPHY driver, >> so fine to leave it. > > Thanks for your work. I would like to test this together with the DSIM > and PHY driver by Michael and Marek. So far the boot hangs when probing > the DSIM, but I'm not even sure if my DT is correct. > > With the DSIM PHY driver (see [1]) in place, the GPR_MIPI_M_RESETN > should be set correctly, right? So I found out, that with the hack below applied (taken from Marek's WIP patches for DSIM support) it seems to work properly. Therefore I guess this is an issue with the DSIM driver, that somehow needs to make sure that the proper clocks are enabled at probe time. diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 04564017bfe9..5a9bca805b0c 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -9,6 +9,7 @@ */ #include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> @@ -193,6 +194,7 @@ to_imx_pgc_domain(struct generic_pm_domain *genpd) static int imx_pgc_power_up(struct generic_pm_domain *genpd) { struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); + unsigned int i; u32 reg_val; int ret; @@ -254,7 +256,14 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) } /* Disable reset clocks for all devices in the domain */ - clk_bulk_disable_unprepare(domain->num_clks, domain->clks); + //clk_bulk_disable_unprepare(domain->num_clks, domain->clks); + for (i = 0; i < domain->num_clks; i++) { + /* Keep the DISPMIX active, it is needed by both LCDIF and MIPI */ + if (strcmp(__clk_get_name(domain->clks[i].clk), "disp_root_clk") && + strcmp(__clk_get_name(domain->clks[i].clk), "disp_axi_root_clk") && + strcmp(__clk_get_name(domain->clks[i].clk), "disp_apb_root_clk")) + clk_disable_unprepare(domain->clks[i].clk); + } return 0;
From: Peng Fan <peng.fan@nxp.com> V2: Fix yaml check failure Previously there is an effort from Abel that take BLK-CTL as clock provider, but it turns out that there is A/B lock issue and we are not able resolve that. Per discuss with Lucas and Jacky, we made an agreement that take BLK-CTL as a power domain provider and use GPC's domain as parent, the consumer node take BLK-CTL as power domain input. This patchset has been tested on i.MX8MM EVK board, but one hack is not included in the patchset is that the DISPMIX BLK-CTL MIPI_M/S_RESET not implemented. Per Lucas, we will finally have a MIPI DPHY driver, so fine to leave it. Thanks for Lucas's suggestion, Frieder Schrempf for collecting all the patches, Abel's previous BLK-CTL work, Jacky Bai on help debug issues. Peng Fan (4): dt-bindings: power: Add defines for i.MX8MM BLK-CTL power domains Documentation: bindings: clk: Add bindings for i.MX BLK_CTL soc: imx: Add generic blk-ctl driver soc: imx: Add blk-ctl driver for i.MX8MM .../bindings/soc/imx/fsl,imx-blk-ctl.yaml | 73 +++++ drivers/soc/imx/Makefile | 2 +- drivers/soc/imx/blk-ctl-imx8mm.c | 138 ++++++++ drivers/soc/imx/blk-ctl.c | 303 ++++++++++++++++++ drivers/soc/imx/blk-ctl.h | 76 +++++ include/dt-bindings/power/imx8mm-power.h | 11 + 6 files changed, 602 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml create mode 100644 drivers/soc/imx/blk-ctl-imx8mm.c create mode 100644 drivers/soc/imx/blk-ctl.c create mode 100644 drivers/soc/imx/blk-ctl.h