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[0/4] mailbox: imx: add i.MX8ULP MU support

Message ID 20210507101926.25631-1-peng.fan@oss.nxp.com (mailing list archive)
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Series mailbox: imx: add i.MX8ULP MU support | expand

Message

Peng Fan (OSS) May 7, 2021, 10:19 a.m. UTC 
From: Peng Fan <peng.fan@nxp.com>

i.MX8ULP generic MU is a different IP compared with previous i.MX chips.
It has different register layout and bit position, but the register name
and bit definitions are almost same with previous i.MX MU.

So we extend the current imx-mailbox driver to support i.MX8ULP.

Peng Fan (4):
  dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
  mailbox: imx: replace the xTR/xRR array with single register
  mailbox: imx: add xSR/xCR register array
  mailbox: imx-mailbox: support i.MX8ULP MU

 .../devicetree/bindings/mailbox/fsl,mu.yaml   |   1 +
 drivers/mailbox/imx-mailbox.c                 | 196 +++++++++++-------
 2 files changed, 123 insertions(+), 74 deletions(-)

Comments

Peng Fan (OSS) May 26, 2021, 6:06 a.m. UTC | #1 
Hi Jassi, Shawn

On 2021/5/7 18:19, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> i.MX8ULP generic MU is a different IP compared with previous i.MX chips.
> It has different register layout and bit position, but the register name
> and bit definitions are almost same with previous i.MX MU.
> 
> So we extend the current imx-mailbox driver to support i.MX8ULP.

Gentle ping.. Except dt-bindings patch get A-b from Rob,no comments.
Is it ok for you to pick up this patchset?

Thanks,
Peng.

> 
> Peng Fan (4):
>    dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
>    mailbox: imx: replace the xTR/xRR array with single register
>    mailbox: imx: add xSR/xCR register array
>    mailbox: imx-mailbox: support i.MX8ULP MU
> 
>   .../devicetree/bindings/mailbox/fsl,mu.yaml   |   1 +
>   drivers/mailbox/imx-mailbox.c                 | 196 +++++++++++-------
>   2 files changed, 123 insertions(+), 74 deletions(-)
>