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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=ABOnE8EQvUs+g+HO4WSCTrBl6JyePAkDbY8mNJrHYIw=; b=EcvBqVZirxd3Rm07fTS3oasrwzNoNmenYpWhB4/qZk9cyqpz4ld724Mzs3MLIILifu aDUMxa/M+nsyaVL9x4AOIOBP6hwEF0DWSe61XJto4wFDKoaf5RuV7AMzPqu1bIpbL69J Ee1Zps1TXzXXPbP7Nt6EHApX4QfGAZs5fvYvNM6nP/7Wdo+Al+YMSV8MyIWmJeGcaWgN +YrP4+wRIX+vNjUAGEOQW2Osxw5kOGOOqcXwli0CPP2cS74J89YSlxssryIIj3b0hr4y DIC9dGOLJ/0OMFGnqPVdM2GTmA09xpGwWu+dHjBFTJGagItTShFBaXnVtN8pFk1V6BaJ zxyg== X-Gm-Message-State: AOAM533S8GkQgHEZa+ZSsEGhUfWv/WTQmIxs7/LORHgF/mz7e5U8Vg9Q 8IUHEaQzQhAE9BL/05DcJ44Ccu4= X-Google-Smtp-Source: ABdhPJxd4R/aTBYS7k+EtDLGlCq9dGbzqJqqulxeoLOUhTYmtZB0yUGRr+UY1ff9/InCuGth5gL+4lU= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:8b00:104d:c249:d343]) (user=pcc job=sendgmr) by 2002:a25:f40c:: with SMTP id q12mr49466988ybd.478.1625094918095; Wed, 30 Jun 2021 16:15:18 -0700 (PDT) Date: Wed, 30 Jun 2021 16:15:05 -0700 Message-Id: <20210630231509.3773172-1-pcc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.32.0.93.g670b81a890-goog Subject: [PATCH v8 0/4] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis From: Peter Collingbourne To: Catalin Marinas , Vincenzo Frascino , Will Deacon Cc: Peter Collingbourne , Evgenii Stepanov , Szabolcs Nagy , Tejas Belagod , linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210630_161520_417931_6DD387ED X-CRM114-Status: GOOD ( 18.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On some CPUs the performance of MTE in synchronous mode is similar to that of asynchronous mode. This makes it worthwhile to enable synchronous mode on those CPUs when asynchronous mode is requested, in order to gain the error detection benefits of synchronous mode without the performance downsides. Therefore, make it possible for user programs to opt into upgrading to synchronous mode on those CPUs. This is done by introducing a notion of a preferred TCF mode, which is controlled on a per-CPU basis by a sysfs node. The existing SYNC and ASYNC TCF settings are repurposed as bitfields that specify a set of possible modes. If the preferred TCF mode for a particular CPU is in the user-provided mode set (this will always be the case for mode sets containing more than one mode because the kernel only supports two tag checking modes, but future kernels may support more modes) then that mode is used when running on that CPU, otherwise one of the modes in the task's mode set will be selected in a currently unspecified manner. v8: - split into multiple patches - remove MTE_CTRL_TCF_NONE - improve documentation - disable preemption and add comment to mte_update_sctlr_user - bring back PR_MTE_TCF_SHIFT for source compatibility - address formatting nit v7: - switch to new API proposed on list v6: - switch to strings in sysfs nodes instead of TCF values v5: - updated documentation - address some nits in mte.c v4: - switch to new mte_ctrl field - make register_mte_upgrade_async_sysctl return an int - change the sysctl to take 0 or 1 instead of raw TCF values - "same as" -> "similar to" v3: - drop the device tree support - add documentation - add static_assert to ensure no overlap with real HW bits - move per-CPU variable initialization to mte.c - use smp_call_function_single instead of stop_machine v2: - make it an opt-in behavior - change the format of the device tree node - also allow controlling the feature via sysfs Peter Collingbourne (4): arm64: mte: rename gcr_user_excl to mte_ctrl arm64: mte: change ASYNC and SYNC TCF settings into bitfields arm64: mte: introduce a per-CPU tag checking mode preference Documentation: document the preferred tag checking mode feature .../arm64/memory-tagging-extension.rst | 48 +++++- arch/arm64/include/asm/mte.h | 4 + arch/arm64/include/asm/processor.h | 8 +- arch/arm64/kernel/asm-offsets.c | 2 +- arch/arm64/kernel/entry.S | 4 +- arch/arm64/kernel/mte.c | 159 ++++++++++++------ include/uapi/linux/prctl.h | 11 +- 7 files changed, 171 insertions(+), 65 deletions(-)