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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=+v/n+6qljDkjWWqyOdzDA7eNQr2e+J3gwkpYrnBqlDE=; b=nDuHx1lDl0bfGWbaidjJ7B7s7ZNhGxU+MUZ2UHX0SitCO8iZlKInYIDCMi7/MU+6mR op8LNvs4QC2c4w1sFshqIjIrnuW0j5OQS6ZoLSNYrorUsFicUJh7qWQ7iHJcbqyL3HCE 3wieVsoTPuje1bHokfzxZN7gNyia4dmjeDHUbk1JW6BgxawHKKSwqZIGj6y22arX7K0J FGW5JLzVPAIU9aAellMPIdMVaI/43XDTpRMfI/Xk6Wqm4Xf63jpg2LX5Decn+j8RK0pS 64DouUouO1K2/7oXVViNQgKuokCfKW3+5MYsFTF2JYvLSDQ1YR3qPY2/hzApW/+nwj8+ 0Iig== X-Gm-Message-State: AOAM531881qCAZ9uqlXlnbPPd7rxnbwgYh/PV2yl2BesRgCmMFYv4XdX hrU8MruEBGynPypuoWyLcoTmaOY= X-Google-Smtp-Source: ABdhPJyUp+EqOF++dz45DGRAnBcQ0J+y0BIp47kipfk24MBlGv4I02HFTEPEMTxHL5I1SchRUx+4qFM= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:99b9:48f7:dbe6:8670]) (user=pcc job=sendgmr) by 2002:ad4:4bae:: with SMTP id i14mr1201587qvw.24.1626220085279; Tue, 13 Jul 2021 16:48:05 -0700 (PDT) Date: Tue, 13 Jul 2021 16:47:56 -0700 Message-Id: <20210713234801.3858018-1-pcc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.32.0.93.g670b81a890-goog Subject: [PATCH v10 0/5] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis From: Peter Collingbourne To: Catalin Marinas , Vincenzo Frascino , Will Deacon Cc: Peter Collingbourne , Evgenii Stepanov , Szabolcs Nagy , Tejas Belagod , linux-arm-kernel@lists.infradead.org, Greg Kroah-Hartman X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210713_164807_263364_3F7B42F5 X-CRM114-Status: GOOD ( 19.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On some CPUs the performance of MTE in synchronous mode is similar to that of asynchronous mode. This makes it worthwhile to enable synchronous mode on those CPUs when asynchronous mode is requested, in order to gain the error detection benefits of synchronous mode without the performance downsides. Therefore, make it possible for user programs to opt into upgrading to synchronous mode on those CPUs. This is done by introducing a notion of a preferred TCF mode, which is controlled on a per-CPU basis by a sysfs node. The existing SYNC and ASYNC TCF settings are repurposed as bitfields that specify a set of possible modes. If the preferred TCF mode for a particular CPU is in the user-provided mode set (this will always be the case for mode sets containing more than one mode because the kernel only supports two tag checking modes, but future kernels may support more modes) then that mode is used when running on that CPU, otherwise one of the modes in the task's mode set will be selected in a currently unspecified manner. v8: - split into multiple patches - remove MTE_CTRL_TCF_NONE - improve documentation - disable preemption and add comment to mte_update_sctlr_user - bring back PR_MTE_TCF_SHIFT for source compatibility - address formatting nit v7: - switch to new API proposed on list v6: - switch to strings in sysfs nodes instead of TCF values v5: - updated documentation - address some nits in mte.c v4: - switch to new mte_ctrl field - make register_mte_upgrade_async_sysctl return an int - change the sysctl to take 0 or 1 instead of raw TCF values - "same as" -> "similar to" v3: - drop the device tree support - add documentation - add static_assert to ensure no overlap with real HW bits - move per-CPU variable initialization to mte.c - use smp_call_function_single instead of stop_machine v2: - make it an opt-in behavior - change the format of the device tree node - also allow controlling the feature via sysfs Peter Collingbourne (5): arm64: mte: rename gcr_user_excl to mte_ctrl arm64: mte: change ASYNC and SYNC TCF settings into bitfields arm64: move preemption disablement to prctl handlers arm64: mte: introduce a per-CPU tag checking mode preference Documentation: document the preferred tag checking mode feature .../ABI/testing/sysfs-devices-system-cpu | 18 +++ .../arm64/memory-tagging-extension.rst | 48 +++++- arch/arm64/include/asm/pointer_auth.h | 12 +- arch/arm64/include/asm/processor.h | 10 +- arch/arm64/kernel/asm-offsets.c | 2 +- arch/arm64/kernel/entry.S | 4 +- arch/arm64/kernel/mte.c | 139 ++++++++++++------ arch/arm64/kernel/pointer_auth.c | 10 +- arch/arm64/kernel/process.c | 21 +-- include/uapi/linux/prctl.h | 11 +- 10 files changed, 189 insertions(+), 86 deletions(-)