[RFC,v4,0/4] Add Naneng combo PHY support for RK3568

Message

Johan Jonker Dec. 8, 2021, 6:54 p.m. UTC

This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.

=============================================

Changed V4 by Johan Jonker:
  TEST COMPILED ONLY!
  Driver not verified with hardware!
  Produced in the hope that we can get some review progress
  with this serie for the documents and driver.
  Use at your own risk!

  restyle
  add devm_reset_control_array_get()
  remove clk structure
  change refclk DT parse
  change dev_err message
  add dot to phrase
  add ext_refclk variable
  add enable_ssc variable
  rename rockchip_combphy_param_write
  remove param_read
  replace rockchip-naneng-combphy driver name

  rename node name
  remove reset-names
  move #phy-cells
  add rockchip,rk3568-pipe-grf
  add rockchip,rk3568-pipe-phy-grf

=============================================

Changes V3:
  Using api devm_reset_control_get_optional_exclusive and dev_err_probe
  Remove apb_rst
  Redefine registers address
  Move pipe_phy_grf0 to rk3568.dtsi

Changes V2:
  Fix dtschema/dtc warnings/errors
  Using api devm_platform_get_and_ioremap_resource.
  Modify rockchip_combphy_set_Mode.
  Add some PHY registers definition.
  Move phy0 to rk3568.dtsi

Johan Jonker (1):
  dt-bindings: mfd: syscon: add naneng combo phy register compatible

Yifeng Zhao (3):
  dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
  phy: rockchip: add naneng combo phy for RK3568
  arm64: dts: rockchip: add naneng combo phy nodes for rk3568

 .../devicetree/bindings/mfd/syscon.yaml       |   2 +
 .../phy/phy-rockchip-naneng-combphy.yaml      | 127 ++++
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      |  21 +
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  47 ++
 drivers/phy/rockchip/Kconfig                  |   8 +
 drivers/phy/rockchip/Makefile                 |   1 +
 .../rockchip/phy-rockchip-naneng-combphy.c    | 608 ++++++++++++++++++
 7 files changed, 814 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
 create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

Comments

Nicolas Frattaroli Dec. 11, 2021, 7:18 p.m. UTC | #1

On Mittwoch, 8. Dezember 2021 19:54:45 CET Johan Jonker wrote:
> This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.
> 
> =============================================
> 
> Changed V4 by Johan Jonker:
>   TEST COMPILED ONLY!
>   Driver not verified with hardware!
>   Produced in the hope that we can get some review progress
>   with this serie for the documents and driver.
>   Use at your own risk!
> 
>   restyle
>   add devm_reset_control_array_get()
>   remove clk structure
>   change refclk DT parse
>   change dev_err message
>   add dot to phrase
>   add ext_refclk variable
>   add enable_ssc variable
>   rename rockchip_combphy_param_write
>   remove param_read
>   replace rockchip-naneng-combphy driver name
> 
>   rename node name
>   remove reset-names
>   move #phy-cells
>   add rockchip,rk3568-pipe-grf
>   add rockchip,rk3568-pipe-phy-grf
> 
> =============================================
> 

Tested-by: Nicolas Frattaroli <[e-mail]>

Applied this on top of 5.16-rc4, added the necessary device tree
changes to rk356x.dtsi and rk3566-quartz64-a.dts and ran it on
my Quartz64. I tested PCIe2x1 on the one combphy and SATA on the
other, simultaneously. Devices were detected correctly (with some
hiccups on SATA due to a Quartz64 Model A design issue, but it
was detected eventually) and some transfers were done to ensure
it's stable. It is stable.

Regards,
Nicolas Frattaroli