| Message ID | 20220423152403.1681222-1-pgwipeout@gmail.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Enable rk356x PCIe controller | expand |
Looks like your cover letter lacked a "To:" line, which breaks group reply, at least for mutt. On Sat, Apr 23, 2022 at 11:23:58AM -0400, Peter Geis wrote: > This series enables the DesignWare based PCIe controller on the rk356x > series of chips. > We drop the fallback to the core driver due to compatibility issues. > We reset the PCIe controller at driver probe to prevent issues in the > future when firmware / kexec leaves the controller in an unknown state. > We add support for legacy interrupts for cards that lack MSI support > (which is partially broken currently). > We then add the device tree nodes to enable PCIe on the Quartz64 Model > A. > > Patch 1 drops the snps,dw,pcie fallback from the dt-binding > Patch 2 resets the PCIe controller to prevent configuration bugs > Patch 3 adds legacy interrupt support to the driver > Patch 4 adds the device tree binding to the rk356x.dtsi > Patch 5 enables the PCIe controller on the Quartz64-A > > Changelog: > v8: > - add core reset patch > - simplify irq enable/disable functions > - drop spinlock > - only enable/disable irq requested > - only pass the irq register bits used to irq functions > > Changelog: > v7: > - drop assigned-clocks > > v6: > - fix a ranges issue > - point to gic instead of its > > v5: > - fix incorrect series (apologies for the v4 spam) > > v4: > - drop the ITS modification, poor compatibility is better than > completely broken > > v3: > - drop select node from dt-binding > - convert to for_each_set_bit > - convert to generic_handle_domain_irq > - drop unncessary dev_err > - reorder irq_chip items > - change to level_irq > - install the handler after initializing the domain > > v2: > - Define PCIE_CLIENT_INTR_STATUS_LEGACY > - Fix PCIE_LEGACY_INT_ENABLE to only enable the RC interrupts > - Add legacy interrupt enable/disable support > > Peter Geis (5): > dt-bindings: pci: remove fallback from Rockchip DesignWare binding > PCI: dwc: rockchip: reset core at driver probe > PCI: dwc: rockchip: add legacy interrupt support > arm64: dts: rockchip: add rk3568 pcie2x1 controller > arm64: dts: rockchip: enable pcie controller on quartz64-a Please make your subjects and commit logs match previous history: PCI: fu740: Remove unused assignments PCI: kirin: Remove unused assignments PCI: fu740: Force 2.5GT/s for initial device probe PCI: imx6: Assert i.MX8MM CLKREQ# even if no device present PCI: imx6: Invoke the PHY exit function after PHY power off PCI: dwc: Restore MSI Receiver mask during resume PCI: fu740: Drop redundant '-gpios' from DT GPIO lookup PCI: imx6: Enable i.MX6QP PCIe power management support PCI: qcom: Add SM8450 PCIe support PCI: qcom: Add ddrss_sf_tbu flag PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg No "dwc:" (no need to include all path elements; "dwc" isn't relevant unless changing the dwc core itself). Capitalize first word after the driver name ("Reset", "Add"). Wrap commit logs to fill 75 columns. Use blank lines to separate paragraphs. In subjects, commit logs, comments, log messages, etc: s/pcie/PCIe/ s/irq/IRQ/ Wrap code to fit in 80 columns to match the rest of the file (except things like printk strings where it would reduce greppability). > .../bindings/pci/rockchip-dw-pcie.yaml | 12 +- > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 34 ++++++ > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 52 ++++++++ > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 114 +++++++++++++++--- > 4 files changed, 185 insertions(+), 27 deletions(-) > > -- > 2.25.1 >
On Samstag, 23. April 2022 17:23:58 CEST Peter Geis wrote: > This series enables the DesignWare based PCIe controller on the rk356x > series of chips. > We drop the fallback to the core driver due to compatibility issues. > We reset the PCIe controller at driver probe to prevent issues in the > future when firmware / kexec leaves the controller in an unknown state. > We add support for legacy interrupts for cards that lack MSI support > (which is partially broken currently). > We then add the device tree nodes to enable PCIe on the Quartz64 Model > A. Tested-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Tested on a PINE64 Quartz64 Model A. The series was applied to 5.18-rc4, and two devices were tested: Device #1: ASMedia Technology Inc. ASM1142 USB 3.1 Host Controller A USB 3.1 flash drive was plugged into the PCIe USB controller card. Then, the block device was read. Performance was nominal, no errors showed up in dmesg. Device #2: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 03) behind a PLX Technology, Inc. PEX 8608 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba) PCIe switch. (it's a weird card I grabbed off an auction site with both USB and SATA behind a PCIe switch, it's best not to worry about the twisted mind that came up with it.) A USB 3.1 flash drive was plugged into the PCIe controller card's USB 3.0 port. Then, the block device was read. Performance was nominal, no errors appeared in dmesg. 512 megabytes of /dev/urandom were redirected into a file. The file was SHA1 checksummed. The file was then copied onto the mounted USB 3.1 drive which was connected to the PCIe card. The drive was unmounted, then re-mounted, and then a sha1sum of the file on the drive was calculated. The checksums matched. Based on these tests it is my understanding that this patch series is functional for the use cases I have covered. Regards, Nicolas Frattaroli