From patchwork Thu May 19 12:55:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12854923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A551EC433EF for ; Thu, 19 May 2022 12:59:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=uJlKNRZadL6ZGkp3IJxj8sgEsc6X+mqMznfGMDN1F14=; b=1Tyyq3LH9gLJTU uJYgI2U4iOZPOnMbjMbWpp2ExtByr58sGT1Nf9lW05rm+PIolMMu5SONH2wdZ9ykvld3Vuoz5FaWW cvfWVdlKc8lu0DWGF0VWQxBQDEoy75cfi5lHy+LzOHlJROAd2uyljkneneLXTirIawcQ0LnYcqeJr IfzFLSaS5Oex5mKd1nwrZxLrHGH6j8X0hr2Z+34q34lU3AJZ4M1wDGNs070bcowWFrwiqmr/sWRJm rivLiD3wAG2L9tR0D3UeVW2NKniTbFYu3maOzJLWHYbYwRb2GvoVaGuiLcYdJm8H585PxRKGoJdc4 uC4G/aSnoq3Rt/JDlY4w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrfj4-006ok2-L7; Thu, 19 May 2022 12:57:59 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrfgu-006nI7-IU; Thu, 19 May 2022 12:55:46 +0000 X-UUID: 41e945ae4b3e4c6bbd936269fb90edc3-20220519 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:1f04132d-507c-4aa6-843e-7400639d2947, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:2a19b09, CLOUDID:168ccfe2-edbf-4bd4-8a34-dfc5f7bb086d, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:0,BEC:nil X-UUID: 41e945ae4b3e4c6bbd936269fb90edc3-20220519 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1071374789; Thu, 19 May 2022 05:55:31 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 May 2022 05:55:30 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 19 May 2022 20:55:28 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 19 May 2022 20:55:28 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v7 00/19] Cleanup MediaTek clk reset drivers and support SoCs Date: Thu, 19 May 2022 20:55:08 +0800 Message-ID: <20220519125527.18544-1-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220519_055544_692533_7778B713 X-CRM114-Status: GOOD ( 12.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In this series, we cleanup MediaTek clock reset drivers in clk/mediatek folder. MediaTek clock reset driver is used to provide reset control of modules controlled in clk, like infra_ao. Changes for v7: 1. v7 is based on linux-next next-20220519 and Chen-Yu's series[1]. 2. Add support for MT8186. [1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=643003 Changes for v6: 1. Add a new patch to support inuput argument index mode. 2. Revise definition in reset.h to index. Rex-BC Chen (19): clk: mediatek: reset: Add reset.h clk: mediatek: reset: Fix written reset bit offset clk: mediatek: reset: Refine and reorder functions in reset.c clk: mediatek: reset: Extract common drivers to update function clk: mediatek: reset: Merge and revise reset register function clk: mediatek: reset: Revise structure to control reset register clk: mediatek: reset: Support nonsequence base offsets of reset registers clk: mediatek: reset: Support inuput argument index mode clk: mediatek: reset: Change return type for clock reset register function clk: mediatek: reset: Add new register reset function with device clk: mediatek: reset: Add reset support for simple probe dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 dt-bindings: reset: mediatek: Add infra_ao reset index for MT8192/MT8195 clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195 arm64: dts: mediatek: Add infra #reset-cells property for MT8192 arm64: dts: mediatek: Add infra #reset-cells property for MT8195 dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186 dt-bindings: arm: mediatek: Add #reset-cells property for MT8186 clk: mediatek: reset: Add infra_ao reset support for MT8186 .../mediatek/mediatek,mt8186-sys-clock.yaml | 3 + .../mediatek/mediatek,mt8192-sys-clock.yaml | 3 + .../mediatek/mediatek,mt8195-sys-clock.yaml | 3 + arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 + arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +- drivers/clk/mediatek/clk-mt2701-eth.c | 10 +- drivers/clk/mediatek/clk-mt2701-g3d.c | 10 +- drivers/clk/mediatek/clk-mt2701-hif.c | 10 +- drivers/clk/mediatek/clk-mt2701.c | 22 +- drivers/clk/mediatek/clk-mt2712.c | 22 +- drivers/clk/mediatek/clk-mt7622-eth.c | 10 +- drivers/clk/mediatek/clk-mt7622-hif.c | 12 +- drivers/clk/mediatek/clk-mt7622.c | 22 +- drivers/clk/mediatek/clk-mt7629-eth.c | 10 +- drivers/clk/mediatek/clk-mt7629-hif.c | 12 +- drivers/clk/mediatek/clk-mt8135.c | 22 +- drivers/clk/mediatek/clk-mt8173.c | 22 +- drivers/clk/mediatek/clk-mt8183.c | 18 +- drivers/clk/mediatek/clk-mt8186-infra_ao.c | 23 ++ drivers/clk/mediatek/clk-mt8192.c | 29 +++ drivers/clk/mediatek/clk-mt8195-infra_ao.c | 24 +++ drivers/clk/mediatek/clk-mtk.c | 7 + drivers/clk/mediatek/clk-mtk.h | 9 +- drivers/clk/mediatek/reset.c | 198 +++++++++++++----- drivers/clk/mediatek/reset.h | 82 ++++++++ include/dt-bindings/reset/mt8186-resets.h | 5 + include/dt-bindings/reset/mt8192-resets.h | 8 + include/dt-bindings/reset/mt8195-resets.h | 6 + 28 files changed, 522 insertions(+), 94 deletions(-) create mode 100644 drivers/clk/mediatek/reset.h Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado