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[23.90.200.126]) by smtp.googlemail.com with ESMTPSA id o5-20020a5d62c5000000b00228cbac7a25sm13998628wrv.64.2022.10.19.07.03.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 07:03:17 -0700 (PDT) Subject: [PATCH v3 0/2] spi: amlogic: meson-spicc: Use pinctrl to drive CLK line when idle MIME-Version: 1.0 X-b4-tracking: H4sIAB4DUGMC/3WNzQrCMBCEX6Xs2ZV0q/bn5HuIh01c7UKalsQWS+m7G7x7Gr6Bb2aDJFElQVdsEG XRpGPIUB0KcD2Hl6A+MgMZotKYE84T8uDxqR9Mk6Ija2upG7mYCrJkOQnayMH1WQuz97nsNb3HuP5O Fspx+7u3EBqspGFpSy5bOl8tr15tlKMbB7jv+/4FlmtKQLQAAAA= From: Amjad Ouled-Ameur Date: Wed, 19 Oct 2022 16:01:02 +0200 Message-Id: <20221004-up-aml-fix-spi-v3-0-89de126fd163@baylibre.com> To: Mark Brown , Neil Armstrong , Krzysztof Kozlowski , Jerome Brunet , Martin Blumenstingl , Kevin Hilman , Rob Herring Cc: Da Xue , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, Neil Armstrong , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Amjad Ouled-Ameur X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1666188196; l=1508; i=aouledameur@baylibre.com; s=20220920; h=from:subject:message-id; bh=/olsUtwOJnRswdLM6doMxbVMNoGB8qZCnkiNegDbh1w=; b=aFPV+HsjpwaTDlj7ngssvgjXRK+U0pQ5Yu0g/7m9QFR2MBhDYQYr2iRBsvSx6x+PD6M/5IKDkRss MTCh+avjCw3BKpkSwtHHwbLoGKJbXu2qDxoOXZfjOz5/8jYPCtQC X-Developer-Key: i=aouledameur@baylibre.com; a=ed25519; pk=HgYWawSL4qLGPx+RzJ+Cuu+V8Pi/KQnDDm1wjWPMOFE= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221019_070321_265296_B355CA67 X-CRM114-Status: GOOD ( 13.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Between SPI transactions, all SPI pins are in HiZ state. When using the SS signal from the SPICC controller it's not an issue because when the transaction resumes all pins come back to the right state at the same time as SS. The problem is when we use CS as a GPIO. In fact, between the GPIO CS state change and SPI pins state change from idle, you can have a missing or spurious clock transition. Set a bias on the clock depending on the clock polarity requested before CS goes active, by passing a special "idle-low" and "idle-high" pinctrl state and setting the right state at a start of a message. Signed-off-by: Amjad Ouled-Ameur --- Changes in v3: - Fixed documentation by removing pinctrl states as they are not mandatory. - Link to v2: https://lore.kernel.org/r/20221004-up-aml-fix-spi-v2-0-3e8ae91a1925@baylibre.com --- Amjad Ouled-Ameur (2): spi: dt-bindings: amlogic, meson-gx-spicc: Add pinctrl names for SPI signal states spi: meson-spicc: Use pinctrl to drive CLK line when idle .../bindings/spi/amlogic,meson-gx-spicc.yaml | 67 ++++++++++++++-------- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 14 +++++ drivers/spi/spi-meson-spicc.c | 39 ++++++++++++- 3 files changed, 94 insertions(+), 26 deletions(-) --- base-commit: aae703b02f92bde9264366c545e87cec451de471 change-id: 20221004-up-aml-fix-spi-c2bb7e78e603 Best regards,