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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Jan Petrous , Ondrej Spacek , Ghennadi Procopciuc Cc: Chester Lin , netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger Subject: [PATCH 0/5] Add GMAC support for S32 SoC family Date: Mon, 31 Oct 2022 18:10:47 +0800 Message-Id: <20221031101052.14956-1-clin@suse.com> X-Mailer: git-send-email 2.37.3 X-ClientProxiedBy: TYAPR01CA0199.jpnprd01.prod.outlook.com (2603:1096:404:29::19) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0402MB3439:EE_|VE1PR04MB7261:EE_ X-MS-Office365-Filtering-Correlation-Id: 1b195687-2530-4c00-a951-08dabb283a34 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YbLhmO3JihayK/2Adp8H4nv+sZ8JwnFRCJ4SJE2qGq1uX9dOrmMyab1e3BfeUj8Bv1caozAEqku0jim6q1WZjzlGG9/opNqR1u2K29M82dusKaHm3F5Rl4nfYOF63oYVz6b5FQQnFpE4/bh1AxKZFPvcZpT5mJdKwkLm6MdtiEeyiaCK9IVbUJixQPwLCPQxKF6bHipXCD8SF2/YmIJMsXc1BelBBEfYnmg2Kvm49Gq5GWPyMUVXmtyCjVuaVF5HxX1kJIYUNcXKUJZ7QzL3gi+UKmvvKSl+WGQ4gz6Pn76l/3337w7HVEFyfikRXsXuOlvZu60zKSzCrFkchjN1ASN6wuDVbVYIh9lsY4yJpBmVvRLXPLv6YKoG6LRY0+LQouKSpffj43tAHGOouqtUt0rqunm3ZF2SxVcRX0J6EnRue7vvtqlPInAYP0utxbD6E/Wml+tQodmqM5lJPdV2R/Ud44x6u4Lk1DSIiptKfAteGZmWWm21fDwSZ7WYji4bwlEv2+HjVzKAPlZyqDneXdOkH9OxXf8m/pBwA6xYZIltFjkJSj1L2HizACKV0dy/1/6ce9rGWrgbHsJyKaphTzmyAgpccgNHyQLPPrCG0WVjHgtAUmyxXXlnGt7neVtSXNLXGJ71gJ4XISvNBY1+gDcdV2MMkQVOiJ/d2mGHpkcqOn6NP3djlr+r9PoVpapGJml17rAkhLShr5ddp/v194eWz9WMBq8GHvegNSzCl0eEJSVoCPHP4QNpMbEXHF4bbyJ/lemevSxLonmN1JIZlA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI1PR0402MB3439.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(136003)(396003)(39850400004)(376002)(366004)(346002)(451199015)(6486002)(107886003)(966005)(478600001)(66899015)(110136005)(54906003)(316002)(6666004)(86362001)(8676002)(6506007)(4326008)(66476007)(66946007)(66556008)(2906002)(26005)(38100700002)(41300700001)(6512007)(2616005)(186003)(1076003)(83380400001)(8936002)(921005)(36756003)(7416002)(5660300002);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WAwGOjTk87zztHpGrINmD1Mk4/tkaSbI2PwTENy+xhrdZbtN+7ZEUGWF32E0iAIZCdKHKSZUUVBt0w0XY5KsKMYvtg5cpIsX3g9U1eaAL9KMbSw2b6BHFhyG31GV2ZF7dhO00jcSt/N1LWRtMRDbDm9Mp+mhJPLxI8VbCaP/b7VB4Qa/kXpdJhh7KZi5ljONtC1UGtADfiqlqv0l792saY4tPeqYvz0DtMivE/mhLgryD6DLFom5ueKbgtkTnBPJYeb8jT8r3Scqevnwod370GDNqU8yPwFvisnVymunPH2U6jlgvULqNvjZimZAju5ZawY3YTXk0YNv6Pl+sFZnNQRP4jPjUw/x03XlDt9pxhCvMhXNWAwNyiyYi/VhpGzEJREOIwYvL+gcz/KpgqVMyav4JDdCS8Clfevf8WYxdJ5qRlUT6swSL/dPQsub6dtqxunN5AmykYuTEpq8TqWk7j0iZ4lRZhxsHjIqHACPzYWwDbL9AxsyY49xWYG5epbco8TjQY+kSkjzgfMAQ8xjqwbt3z7YIhKrLwHKHVUAes3xGkU5bG2UR/HcYHHDjfl49LCusGpSSGLcRSY9KtKC1W+PgEaTq7YF4mn9/wQoEFg/NIfGzC3HR298C3if61R0Gc0H3ViAVsKBIUFoSiVtXZwfL0bPjAXd145iCJ/4bcRiHrRjq2i8chge87Xrruqh9BbkWUjIpcxQbd+a2Pg9xsrWXDNU4+dTaazFmq1OpF6CzrBnt40M35UmC1E8tILL1HGv/Qx3/p1aW0303sqH9eC8bQIVCFFsnbQTtzaZT1DGqDm/kBXNpbtXbvJI4IjTrvdwnnV2zizUBPtMvVgcwySXCekwReRwMa+LDQmNZAiyapHV1BUk6I1BXsVmvGohdRwQyiuTfnWFV32eQFxNGBqtuaUL0wJ3FO6cwhfIUj5Pu+zXiVh4xBWULIAhsrevBn4faMI3y9tmAmQlt3vJwwPe5OK1S0xbKRdJokXt+n5TzaQ03Q1RNYmB3Don5iMc322G7ZcDmo/TNe4lpguvcEFvhuouXBGArxzLH+xXf1cN3ukg23EVGU3+mM+RzqfR7ukyJkg0xbXRP/AKAa2UrMzxKgYsFjszH9MRkWCsvxI76s/fq9hpLNCcbv1fW/d7+DY0d6KwvzGFld9RuXVLAixluEVhHCDtdTBWR+/BBuEmWW6GYW//pS9FxXgI2F53WLYJBY88FsYqefq7wvAaJwm7l0NLDNmkoriNxd2hOBivvP8pftCsvU8Wo3AlWuaJzCF4mm/29KFT7fJXkwDp898g2HXvaqZEO9ZB/yXcW6MOHvWe+1OI8A79GcUpqaPeMWgytXZmMaIm/pJ79N6yjVdrcG+gOJdx9/Qh4A4N7+iaqCFOqd8+Ws6gwJYB+PhHp1ZgQTIFmYYHCxjEesWrAHurArXAoxwADpS8Tq70BmKDkjG0xYX3xn8nDBgx1tm/T6GMA4xm3JiwgtMkXfXabMAtozKt7RDzifZ1Q22lVl1S7gQ93t+hcUlus3SiTydFRBbTMbt25mvheFE6ZsGSdLAmthIGnxCzlI/CjqOJ5I8= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1b195687-2530-4c00-a951-08dabb283a34 X-MS-Exchange-CrossTenant-AuthSource: VI1PR0402MB3439.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 10:11:07.6899 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 0oOojdLGcpzE0AO97WJ53rqsqQvKjGjRoWtQ7lit4ypWkJIUCtWGX2UEb3GxGu/B X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB7261 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221031_031112_490088_A1E3FFCA X-CRM114-Status: GOOD ( 14.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello, Here I want to introduce a new patch series, which aims to support GMAC functions on S32 SoCs, such as S32G2. This series is originally from NXP's implementation on CodeAurora[1] and it will be required by upstream kernel to configure platform settings at the DWMAC glue layer before activating the DWMAC core on different S32G boards. In this patchset I also introduce more register fields needed by S32 SoCs, such as higher CSR clock ranges and cache coherency settings. For more information please see NXP's GMACSUBSYS Reference Manual[2]. Currently, the whole architecture relies on FDTs offered by ATF[3] on CodeAurora to keep the flexibility of handling multiple S32 platforms since now S32 clks can be triggered via the ARM SCMI clock protocol and clk IDs/ settings can vary according to different board designs. To ensure that the driver can work properly, the dt-binding schemas in this patchset is still required as a reference. Thanks, Chester [1] https://source.codeaurora.org/external/autobsps32/linux/tree/drivers/net/ethernet/stmicro/stmmac?h=bsp34.0-5.10.120-rt [2] https://www.nxp.com/webapp/Download?colCode=GMACSUBSYSRM [3] https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/tag/?h=bsp34.0-2.5 Chester Lin (5): dt-bindings: net: snps, dwmac: add NXP S32CC support dt-bindings: net: add schema for NXP S32CC dwmac glue driver net: stmmac: Add CSR clock 500Mhz/800Mhz support net: stmmac: Add AXI4 ACE control support net: stmmac: Add NXP S32 SoC family support .../bindings/net/nxp,s32cc-dwmac.yaml | 145 ++++++++ .../devicetree/bindings/net/snps,dwmac.yaml | 5 +- drivers/net/ethernet/stmicro/stmmac/Kconfig | 13 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + drivers/net/ethernet/stmicro/stmmac/common.h | 2 + .../net/ethernet/stmicro/stmmac/dwmac-s32cc.c | 318 ++++++++++++++++++ .../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 10 + .../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 4 +- drivers/net/ethernet/stmicro/stmmac/hwif.h | 5 + .../net/ethernet/stmicro/stmmac/stmmac_main.c | 7 + include/linux/stmmac.h | 9 + 11 files changed, 516 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c