From patchwork Thu Nov 3 04:41:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13029528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1064C4332F for ; Thu, 3 Nov 2022 04:42:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=hPAfur3FtxKl6TfaWboIMcngCj7DRc77J7n8eKjuxrs=; b=ccfPIZB2sIBCed ZQneEnbo+tmY21VGwrx29Xtan+d2Q4xSbOAw0bjf0HmHgzi+CIvy5R5USfVnvaNPMCN+Z8G8uduIO yAyEiGGOJo2Bdm+aK4ntjV0B4KuaoN05IxWVJ2b9o8yaspZrj+5ECvoWaJDIPVFmBP4RhyZh//zGn lpYBe9GMRr5KoQTHNfl/SIEZkeCQkL4pC+VjIo186QRrrXrLSqEtwLQO8JM3TYeOSOE38la8qdEWT qOS0mdWmZ2Chfwps9aRM398h7LWqf94DCZaPFB1h3IGPry7Ifzn56mOpNDeRKTjqVgkU9C8TiJUzm L4b7s5N9Hy3iLwKrEBGA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqS2u-00G0NV-Nd; Thu, 03 Nov 2022 04:41:40 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqS2r-00G0Mu-Ux for linux-arm-kernel@lists.infradead.org; Thu, 03 Nov 2022 04:41:39 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A34fWBD112652; Wed, 2 Nov 2022 23:41:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667450492; bh=yts+e6PEG2V1khNQKTTe98rwV6m/Wgusb7LBzdqgrlg=; h=From:To:CC:Subject:Date; b=iYGDh2vRMiIJdDct2zzdfRjHA/xRJ0SRQi2TE5jas8wAbkYgi8d8DTqJlDg5jzb8j k1GnsNSGi7f5fJHV3nVB4y0oPCKTup7YU6Vl2FdxFFJriViT2VKaVdUyi0wm9fAXID eBSoFF/a/T5stfExsIOQLO+UP+qG71mOWBVBtPRw= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A34fW4N041721 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Nov 2022 23:41:32 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 2 Nov 2022 23:41:32 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 2 Nov 2022 23:41:31 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A34fRdU016655; Wed, 2 Nov 2022 23:41:30 -0500 From: Matt Ranostay To: , , , , CC: , Subject: [PATCH v5 0/8] J721S2: Add support for additional IPs Date: Wed, 2 Nov 2022 21:41:17 -0700 Message-ID: <20221103044125.172864-1-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221102_214138_117739_5F28A5EC X-CRM114-Status: GOOD ( 11.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The following series of patches add support for the following on J721S2 common processor board, - USB - SerDes - OSPI - PCIe Changes from v1: * Resolve issues with dt schema reporting * Minor changes related to consistency on node naming and value Changes from v2: * Added PCIe RC + EP enablement patchsets * Added device-id for j722s2 PCIe host in dt documentation * Reworked SERDES + WIZ enablement patchset to use properies for clocks defines versus entire devicetree nodes. Results in cleaner code that doesn't break dt-schema or the driver functionality. Changes from v3: * Rebased changes on top of '[PATCH 00/12] TI J7x Disable Incomplete DT Nodes' * Removed "dt-bindings: PCI: Add host mode device-id for j721s2 platform" patch and send it own series to avoid a dependency that would hold up other patches in this series Changes from v4: * Add my Signed-off-by lines to all patchsets Aswath Govindraju (7): arm64: dts: ti: k3-j721s2-main: Add support for USB arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Matt Ranostay (1): arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node .../dts/ti/k3-j721s2-common-proc-board.dts | 92 +++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 156 ++++++++++++++++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 42 +++++ 4 files changed, 330 insertions(+)