From patchwork Wed Nov 9 08:25:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13037248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DB5DC4332F for ; Wed, 9 Nov 2022 08:27:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=+dDxoVrgf/SiR3r7QVgiEYPIsqEqgf/EDRjN7YReIv0=; b=eXJYg6i68dBlhe oVln2ZYqcnganuxcAdBmLeD15LXI45M1f+yGibRV6iiEf9Wl+HVnzy4I3Ng00h4JGC+QVPZkj16B7 x/0V5ZGi83LLrDTMDitK8JXqUtSX2nBmPq1OdqhHQGaWPfRTdjICuWRTaT7NxJZvAwH7JlscvwMRa r7SVOoJc/8pYViMhvmgHEU6zfCsg+CDG8x4GjhrYOWsGZ85OOWRUv/ZIAxe9LPtju1+zmJNXBauJt aAj8OB7FRcxnwuTefH3n6ajn5xMhOSR20egAo4lyVeODW2BGVMryOorl70VlY/pQIKAjvX6N4/coo qsUY9DfrqJy7QOPBBNqg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1osgPa-00BsiU-RG; Wed, 09 Nov 2022 08:26:18 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1osgPW-00BshN-VG for linux-arm-kernel@lists.infradead.org; Wed, 09 Nov 2022 08:26:16 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A98Q1tP052743; Wed, 9 Nov 2022 02:26:01 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667982361; bh=mo5PdU3cTV74KFAnDyxjJPzU2AfRa0t29F94To7rIac=; h=From:To:CC:Subject:Date; b=k+xjjFoha8h35yW79n3e1JvSiNer5SUlQF6hbcwGnUQHU5wbwefLwYzijeCgQR9X9 rr092HlC0NvjwEaIqKlQGfvpGmLA/j+8dU0skDFH921zIp0PvOlJw+k5IKG6R3Eir3 57LpsDygUhoP2XsVpaTYkV4UoygoSdUFDy/caXYc= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A98Q1ux007564 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Nov 2022 02:26:01 -0600 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 9 Nov 2022 02:26:00 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 9 Nov 2022 02:26:00 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A98PvR3106309; Wed, 9 Nov 2022 02:25:59 -0600 From: Matt Ranostay To: , , , , CC: , , Matt Ranostay Subject: [PATCH v5 0/4] PCI: add 4x lane support for pci-j721e controllers Date: Wed, 9 Nov 2022 00:25:52 -0800 Message-ID: <20221109082556.29265-1-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221109_002615_128955_DE891E66 X-CRM114-Status: UNSURE ( 9.43 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adding of dditional support to Cadence PCIe controller (i.e. pci-j721e.c) for up to 4x lanes, and reworking of driver to define maximum lanes per board configuration. Changes from v1: * Reworked 'PCI: j721e: Add PCIe 4x lane selection support' to not cause regressions on 1-2x lane platforms Changes from v2: * Correct dev_warn format string from %d to %u since lane count is a unsigned integer * Update CC list Changes from v3: * Use the max_lanes setting per chip for the mask size required since bootloader could have set num_lanes to a higher value that the device tree which would leave in an undefined state * Reorder patches do the previous change to not break bisect * Remove line breaking for dev_warn to allow better grepping and since no strict 80 columns anymore Changes from v4: * Correct invalid settings for j7200 PCIe RC + EP * Add j784s4 configuration for selection of 4x lanes Matt Ranostay (4): PCI: j721e: Add per platform maximum lane settings PCI: j721e: Add PCIe 4x lane selection support PCI: j721e: add j784s4 PCIe configuration PCI: j721e: Add warnings on num-lanes misconfiguration drivers/pci/controller/cadence/pci-j721e.c | 51 +++++++++++++++++++--- 1 file changed, 46 insertions(+), 5 deletions(-)