From patchwork Tue Nov 15 15:03:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13043810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3F96C433FE for ; Tue, 15 Nov 2022 15:05:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=C+JWZ3O7+PSDoWLQ6igd3UVrULS+AuuCN1AFOqPn1LE=; b=XDUyttcUpxx6ha Hwfm5PGxeN4Xzjy8iHaYKdk9FqiHzjHGD4Szl4E96iWikJomlPdT3bs4HrgHLlTcogMJneLz1qJsV QuCFreyBhm880VfC4fZaxYCtk5RcvRl18FAyvCas2QN8Upc5eZm15/UGZxBJYEkG5xLcxso0TVatP t11ZxCU8d1bJtCHYqBT/DpQ/Ni8kcuwJ+8T5zH5DkhDNTjDjP14KmWIXopu6TfYQNm67i0BfFo6tv ff2vojNw0dlr4qJcnRkZEBZ8Xk+HdUqLm7iIErriVtZUo2N8xmHky3b84b2fSpRZmiYuL/TGeIQX9 ZkET876eCxJax64Z+JPg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ouxU9-00C9Gp-5p; Tue, 15 Nov 2022 15:04:25 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ouxU6-00C9A5-1H for linux-arm-kernel@lists.infradead.org; Tue, 15 Nov 2022 15:04:23 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AFF3eHM053364; Tue, 15 Nov 2022 09:03:40 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1668524620; bh=QZDPlnaVNc4u9j6ZbxoN1qd/EaOnUupP78tgGX2bqnI=; h=From:To:CC:Subject:Date; b=I1X1SC0vgTUBYaKCYNB/5r9mdxT1HX7aGss6S1heyEdCHAGyVMnswCcRpdXfv/T0K dSXNwI1BlQoXwM8kNGbGjSH8NNVEkIVSHx6QtjYFP/p2R8NFcLwTIqt5efg52j3WVL 1u3Y/0nJkIo6JOTL+4nryiq+5pGbH2QdZoxrRYfI= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AFF3ew9017276 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 15 Nov 2022 09:03:40 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 15 Nov 2022 09:03:40 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 15 Nov 2022 09:03:40 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AFF3aBk049373; Tue, 15 Nov 2022 09:03:38 -0600 From: Matt Ranostay To: , , , , CC: , , Matt Ranostay Subject: [PATCH v6 0/5] PCI: add 4x lane support for pci-j721e controllers Date: Tue, 15 Nov 2022 07:03:30 -0800 Message-ID: <20221115150335.501502-1-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221115_070422_198510_F59FB829 X-CRM114-Status: UNSURE ( 8.82 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adding of dditional support to Cadence PCIe controller (i.e. pci-j721e.c) for up to 4x lanes, and reworking of driver to define maximum lanes per board configuration. Changes from v1: * Reworked 'PCI: j721e: Add PCIe 4x lane selection support' to not cause regressions on 1-2x lane platforms Changes from v2: * Correct dev_warn format string from %d to %u since lane count is a unsigned integer * Update CC list Changes from v3: * Use the max_lanes setting per chip for the mask size required since bootloader could have set num_lanes to a higher value that the device tree which would leave in an undefined state * Reorder patches do the previous change to not break bisect * Remove line breaking for dev_warn to allow better grepping and since no strict 80 columns anymore Changes from v4: * Correct invalid settings for j7200 PCIe RC + EP * Add j784s4 configuration for selection of 4x lanes Changes from v5: * Dropped 'PCI: j721e: Add warnings on num-lanes misconfiguration' patch from series * Reworded 'PCI: j721e: Add per platform maximum lane settings' commit message * Added yaml documentation and schema checks for ti,j721e-pci-* lane checking Matt Ranostay (5): dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes PCI: j721e: Add per platform maximum lane settings PCI: j721e: Add PCIe 4x lane selection support dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings PCI: j721e: add j784s4 PCIe configuration .../bindings/pci/ti,j721e-pci-ep.yaml | 40 +++++++++++++++-- .../bindings/pci/ti,j721e-pci-host.yaml | 42 ++++++++++++++++-- drivers/pci/controller/cadence/pci-j721e.c | 44 ++++++++++++++++--- 3 files changed, 115 insertions(+), 11 deletions(-)