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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Jan Petrous , Ondrej Spacek , Ghennadi Procopciuc , Andrew Lunn Cc: Chester Lin , netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger Subject: [PATCH v2 0/5] Add GMAC support for S32 SoC family Date: Mon, 28 Nov 2022 13:49:15 +0800 Message-Id: <20221128054920.2113-1-clin@suse.com> X-Mailer: git-send-email 2.37.3 X-ClientProxiedBy: TYCP286CA0137.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:31b::15) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0402MB3439:EE_|AS8PR04MB7655:EE_ X-MS-Office365-Filtering-Correlation-Id: fb54f2ea-b861-4aee-d3ed-08dad1045020 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aKUPmmD5RQ/H38ZRtf+LOWewRTybgjHSyjpEOn3DzRhWvgTYoTzhQJwGlR73AcNJ0y9zcmX4MkNexwU7bL1mpG7frAMTf/7HWAZ+Lc2mbcLE4+3Bs7scN+2D17x8bxOvBiITvSG9B2rBwcEjOBUBN48uv3DIAEACDF/sCjfIThJi8lfba/hRhxnvRvgA2Ei3FZrQ0Sm7b2t0GYpS1dJP78AlV+kM6NJOF0h1QJxaogOHvXf2YQiKPLLXONXCEPd38nW4Y44xFp+8/do3ul/LaKoX6MA6pQy2q857b6JQWRFqml1pWbWlKGiE53piKwexYobS/PhHKrwMhlVS6jtGfFzde1PHJswuBTyqNCUznF09WXmzQeTmZBry534NxOtIluROi5qRU6vrEAua9+fYoct/+0L330Z0s+1/kI9ofWHFlZaARypJ7BqSnxKZS+aNLValfkWS0eWPSeH6oEi7hLHK/3j+VnGxpoGK8sgRBY5R9DI1fGaGXcQ1EFfWI1kh1QabcB8VUFpduwgMvfzf0CDSBTZsjairKjA3/lcLaSVWUAcZuxpSuULnzYZG6+fW9r4asR781GnAf1WO4bg324NNg/IJkhkArjpDowIKNp33gzYtv/czooA3J0Po17Z0e84Kst6Co38V8o0TkgmSX6sOhtAoDjbb6Vm0WWayfbgpp4jBVAP54YPTGjixmxvIqo8W9/AxwrYyOFWrInE8sA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI1PR0402MB3439.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(39860400002)(366004)(346002)(136003)(396003)(376002)(451199015)(2616005)(6506007)(6512007)(36756003)(7416002)(1076003)(186003)(5660300002)(54906003)(86362001)(110136005)(66476007)(8676002)(4326008)(66946007)(66556008)(2906002)(41300700001)(38100700002)(316002)(83380400001)(8936002)(478600001)(6486002)(966005)(66899015)(107886003)(6666004)(921005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: K3S0cg5UkjW/YAOdW5oZRVQKZYLktpln4czq+gVpgQg2Hn1G61ZxDLJWkuhMYSuHZErwZQqyfcGbZ7hs7PSuk0MbtIaUvP4tLguuaf3+gkwjrqOimqoU03NyGePfruxL65hKNb2PnwXL2IFo0dKx/+2w9ReCpgCV1Bkcq6bsHw661pSjNa5URcsPT6kqnYM11Del3hVVmTXUat6E1ch8odJoNxvjsKblbo9mawKk7jyPwu0ng4hVxXISmsShmwRsNFRZTjaAt/cE+WCBXXinacYxUjX6Xlgn0KcTUwgoHPAFu4UNtNgmsKqaQw1ZHrTFDfXuemKjQxuh57qwc/ssxS2OIogrgTWeLCtr0S3vn+OWVEsMNo/8kiZgfZrj7N0rdW8KCgZfU6OeoURyC2ppJXJX7RpC3gyiuRbptBEymxw3b+LTQSoYpljnD82XzcNMwA0dISmiNFgE+HvYoTUxLlflzDcOgroofXU/KR07Jl3s9kkE0tsOS/hiqjl963kLGdw07K3iUheFfb2AunqK3qu4eJI7k39V1jiSr5/IxtDh5qk61aWYVLO7nmWgT30D7fDyPMKEO+XpBkGTBdtiKSZ2KpGJhTdgGQgMqCeJFApqwkZmIv6RfAkGzSTXdEmjiC1pOxTC+OOBo8FuWiM5FL0hPa91z2XKe8LIOvD+G/2tuyn96ZWWgLpONbekdh+JEZfQYmXq8vOhtzXclBGJrgCDfva34lwYpejmD/4u0FlDiZ8vyGgOhyBaX8ZdTjFh+ZmtGuawzEjtnSSwv89+51taRaVk2RcXI/Xg86y53FNIhqbqrBFoLvGZ1ShcaG6oyjH3hcqr7iYt1V910gKH9d0Ec1/eZNjLUgBtV3634OAsRSFtfx/CTZntoRmdcfI/SaZLzX7I2lI7CMahUF7BiotSKU+iTTNorxDFrDu370loHrKtXAAqKIcNPfqBRQiwuTg8xCT8TqqCFOyYsckSimOSf9p6lZu0bW2aU+E1Sy9B5FM13yqK7QG1Bpuklx8JYd1CzOMLbkyr5z9iWd/vEN69BJVSyhG7YHxeMznvBawSRCKB5tkBrBYc3pF22J7A210Lz2yUp0X6sSqspll46v50REBq+HLXI6E4VCzul+wBJ4EWUBmq19w/nbZNW7+vIEq4CayY4U0f//x+aIe7L81c66R9QF2IiloYO+M/Er+hKYN4K8kDRhP2VRGerHHXGLbOcGym/tLMU38EuuT381Mk6Y3tKdeICY3oZUPY/m4Nzc2/13L1Q84hgtq8Mw4OFZhDI6BiEA5vPAO/RLgioJNoniBsXnvwA/t5GSF0cfXi/F37l1vwBb8n0sd62p2ZjsGldRR/GkJw0wSBPt5m1PlVckflEWKZUisLCY/hKusCwMY8LS6xMubuT87th1Tf+FTgEjLweSRWftOB6Ujja+HLwYqRuIpA8BF/Qfr7kimXCk3rO0X643R/kgegFNS3DLZ1oalKruNpRy9wysTL/URgGEYY7pp4Ljk2rxoIIHsUCeVfpGVMicuGW8gxjbG1A8yki/JxJq8hxRhM5wGBgx1mbbkGJU+OIPS+i8qt1PtfU8mLJNBAAbt9FxX8GOX4kQitroU94k3CbfASx0a/WY2OdUG1vYSXtvIXrs6JjacnI796qL2+GdqAA5khfRfQ X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: fb54f2ea-b861-4aee-d3ed-08dad1045020 X-MS-Exchange-CrossTenant-AuthSource: VI1PR0402MB3439.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2022 05:49:28.4030 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: cMLEqk8y5Su4XLZjYViyA7cS0aipEFlmmRlpPRCFwZD4aZ77KK9pj4rlBdky0hjv X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB7655 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221127_214933_625959_379AC515 X-CRM114-Status: GOOD ( 16.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello, Here I want to introduce a new patch series, which aims to support GMAC functions on S32 SoCs, such as S32G2. This series is originally from NXP's implementation on CodeAurora[1] and it will be required by upstream kernel to configure platform settings at the DWMAC glue layer before activating the DWMAC core on different S32G boards. In this patchset I also introduce more register fields needed by S32 SoCs, such as higher CSR clock ranges and cache coherency settings. For more information please see NXP's GMACSUBSYS Reference Manual[2]. Currently, the whole architecture relies on FDTs offered by ATF[3] on CodeAurora to keep the flexibility of handling multiple S32 platforms since now S32 clks can be triggered via the ARM SCMI clock protocol and clk IDs/ settings can vary according to different board designs. To ensure that the driver can work properly, the dt-binding schemas in this patchset is still required as a reference. Thanks, Chester Changes in v2: - Fix schema issues. - Add minItems to clocks & clock-names. - Replace all sgmii/SGMII terms with pcs/PCS. - clock-names: tx_sgmii -> tx_pcs, rx_sgmii -> rx_pcs - Adjust error handlings while calling devm_clk_get(). - Remove redundant dev_info messages. - Remove unnecessary if conditions. - Fix the copyright format suggested by NXP. [1] https://source.codeaurora.org/external/autobsps32/linux/tree/drivers/net/ethernet/stmicro/stmmac?h=bsp34.0-5.10.120-rt [2] https://www.nxp.com/webapp/Download?colCode=GMACSUBSYSRM [3] https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/tag/?h=bsp34.0-2.5 Chester Lin (5): dt-bindings: net: snps, dwmac: add NXP S32CC support dt-bindings: net: add schema for NXP S32CC dwmac glue driver net: stmmac: Add CSR clock 500Mhz/800Mhz support net: stmmac: Add AXI4 ACE control support net: stmmac: Add NXP S32 SoC family support .../bindings/net/nxp,s32cc-dwmac.yaml | 135 ++++++++ .../devicetree/bindings/net/snps,dwmac.yaml | 5 +- drivers/net/ethernet/stmicro/stmmac/Kconfig | 13 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + drivers/net/ethernet/stmicro/stmmac/common.h | 2 + .../net/ethernet/stmicro/stmmac/dwmac-s32cc.c | 304 ++++++++++++++++++ .../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 10 + .../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 4 +- drivers/net/ethernet/stmicro/stmmac/hwif.h | 5 + .../net/ethernet/stmicro/stmmac/stmmac_main.c | 7 + include/linux/stmmac.h | 9 + 11 files changed, 492 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c