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Sat, 10 Dec 2022 21:17:25 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id f125-20020a623883000000b00575d90636dcsm3463684pfa.6.2022.12.10.21.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Dec 2022 21:17:25 -0800 (PST) From: Akihiko Odaki To: Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH 0/3] KVM: arm64: Normalize cache configuration Date: Sun, 11 Dec 2022 14:16:57 +0900 Message-Id: <20221211051700.275761-1-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221210_211728_421975_1D4D88CE X-CRM114-Status: GOOD ( 11.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Before this change, the cache configuration of the physical CPU was exposed to vcpus. This is problematic because the cache configuration a vcpu sees varies when it migrates between vcpus with different cache configurations. Fabricate cache configuration from arm64_ftr_reg_ctrel0.sys_val, which holds the CTR_EL0 value the userspace sees regardless of which physical CPU it resides on. HCR_TID2 is now always set as it is troublesome to detect the difference of cache configurations among physical CPUs. CSSELR_EL1 is now held in the memory instead of the corresponding phyisccal register as the fabricated cache configuration may have a cache level which does not exist in the physical CPU, and setting the physical CSSELR_EL1 for the level results in an UNKNOWN behavior. CLIDR_EL1 and CCSIDR_EL1 are now writable from the userspace so that the VMM can restore the values saved with the old kernel. Akihiko Odaki (3): arm64/sysreg: Add CCSIDR2_EL1 arm64/cache: Move CLIDR macro definitions KVM: arm64: Normalize cache configuration arch/arm64/include/asm/cache.h | 6 + arch/arm64/include/asm/kvm_arm.h | 3 +- arch/arm64/include/asm/kvm_emulate.h | 4 - arch/arm64/include/asm/kvm_host.h | 6 +- arch/arm64/kernel/cacheinfo.c | 5 - arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 2 - arch/arm64/kvm/reset.c | 1 + arch/arm64/kvm/sys_regs.c | 232 ++++++++++++--------- arch/arm64/tools/sysreg | 5 + 9 files changed, 153 insertions(+), 111 deletions(-)