| Message ID | 20230109174511.1740856-1-brgl@bgdev.pl (mailing list archive) |
|---|---|
| Headers | show |
| Series | arm64: qcom: add support for sa8775p-ride | expand |
On 9.01.2023 18:44, Bartosz Golaszewski wrote: > From: Shazad Hussain <quic_shazhuss@quicinc.com> > > Add support for the Global Clock Controller found in the QTI SA8775P > platforms. > > Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> > [Bartosz: made the driver ready for upstream] > Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- [...] > + > +static struct gdsc usb20_prim_gdsc = { > + .gdscr = 0x1C004, Please use lowercase hex literals outside #defines. > + .pd = { > + .name = "usb20_prim_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > +}; > + [...] > + > +static const struct regmap_config gcc_sa8775p_regmap_config = { > + .reg_bits = 32, > + .reg_stride = 4, > + .val_bits = 32, > + .max_register = 0x472cffc, This is faaaaar more than what your DT node specifies. With these two fixed, LGTM: Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > + .fast_io = true, > +}; > + > +static const struct qcom_cc_desc gcc_sa8775p_desc = { > + .config = &gcc_sa8775p_regmap_config, > + .clks = gcc_sa8775p_clocks, > + .num_clks = ARRAY_SIZE(gcc_sa8775p_clocks), > + .resets = gcc_sa8775p_resets, > + .num_resets = ARRAY_SIZE(gcc_sa8775p_resets), > + .gdscs = gcc_sa8775p_gdscs, > + .num_gdscs = ARRAY_SIZE(gcc_sa8775p_gdscs), > +}; > + > +static const struct of_device_id gcc_sa8775p_match_table[] = { > + { .compatible = "qcom,gcc-sa8775p" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, gcc_sa8775p_match_table); > + > +static int gcc_sa8775p_probe(struct platform_device *pdev) > +{ > + struct regmap *regmap; > + int ret; > + > + regmap = qcom_cc_map(pdev, &gcc_sa8775p_desc); > + if (IS_ERR(regmap)) > + return PTR_ERR(regmap); > + > + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, > + ARRAY_SIZE(gcc_dfs_clocks)); > + if (ret) > + return ret; > + > + /* > + * Keep the clocks always-ON > + * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK, > + * GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, > + * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK. > + */ > + regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0)); > + > + return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); > +} > + > +static struct platform_driver gcc_sa8775p_driver = { > + .probe = gcc_sa8775p_probe, > + .driver = { > + .name = "gcc-sa8775p", > + .of_match_table = gcc_sa8775p_match_table, > + }, > +}; > + > +static int __init gcc_sa8775p_init(void) > +{ > + return platform_driver_register(&gcc_sa8775p_driver); > +} > +subsys_initcall(gcc_sa8775p_init); > + > +static void __exit gcc_sa8775p_exit(void) > +{ > + platform_driver_unregister(&gcc_sa8775p_driver); > +} > +module_exit(gcc_sa8775p_exit); > + > +MODULE_DESCRIPTION("Qualcomm SA8775P GCC driver"); > +MODULE_LICENSE("GPL");
On 9.01.2023 18:45, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Enable the Qualcomm SA8775P interconnect driver for arm64 builds. It's > required to be built-in for QUPv3 to work early which in turn is needed > for the console. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/configs/defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index 1cb586125c46..d5c938adbd2d 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -1332,6 +1332,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8916=m > CONFIG_INTERCONNECT_QCOM_MSM8996=m > CONFIG_INTERCONNECT_QCOM_OSM_L3=m > CONFIG_INTERCONNECT_QCOM_QCS404=m > +CONFIG_INTERCONNECT_QCOM_SA8775P=y > CONFIG_INTERCONNECT_QCOM_SC7180=y > CONFIG_INTERCONNECT_QCOM_SC7280=y > CONFIG_INTERCONNECT_QCOM_SC8180X=y
On 9.01.2023 18:45, Bartosz Golaszewski wrote: > From: Yadu MG <quic_ymg@quicinc.com> > > Add support for Lemans TLMM configuration and control via the pinctrl > framework. > > Signed-off-by: Yadu MG <quic_ymg@quicinc.com> > Signed-off-by: Prasad Sodagudi <quic_psodagud@quicinc.com> > [Bartosz: made the driver ready for upstream] > Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- [...] > + > +static const char * const gpio_groups[] = { > + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", > + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", > + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", > + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", > + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", > + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", > + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", > + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", > + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", > + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", > + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", > + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", > + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", > + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", > + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", > + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", > + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", > + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", > + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", > + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", > + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", > + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", > + "gpio147", "gpio148", > +}; > +static const char * const atest_char_groups[] = { A newline after };-s would make this consistent with other drivers. [...] > + > +/* Every pin is maintained as a single group, and missing or non-existing pin /* * Every pin With these nits: Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > + * would be maintained as dummy group to synchronize pin group index with > + * pin descriptor registered with pinctrl core. > + * Clients would not be able to request these dummy pin groups. > + */ > +static const struct msm_pingroup sa8775p_groups[] = { > + [0] = PINGROUP(0, _, _, _, _, _, _, _, _, _), > + [1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _), > + [2] = PINGROUP(2, _, _, _, _, _, _, _, _, _), > + [3] = PINGROUP(3, pcie1_clkreq, _, _, _, _, _, _, _, _), > + [4] = PINGROUP(4, _, _, _, _, _, _, _, _, _), > + [5] = PINGROUP(5, _, _, _, _, _, _, _, _, _), > + [6] = PINGROUP(6, emac0_ptp, emac0_ptp, emac1_ptp, emac1_ptp, _, _, _, _, _), > + [7] = PINGROUP(7, sgmii_phy, _, _, _, _, _, _, _, _), > + [8] = PINGROUP(8, emac0_mdc, _, _, _, _, _, _, _, _), > + [9] = PINGROUP(9, emac0_mdio, _, _, _, _, _, _, _, _), > + [10] = PINGROUP(10, usb2phy_ac, emac0_ptp, emac0_ptp, emac1_ptp, emac1_ptp, _, _, _, _), > + [11] = PINGROUP(11, usb2phy_ac, emac0_ptp, emac0_ptp, emac1_ptp, emac1_ptp, _, _, _, _), > + [12] = PINGROUP(12, usb2phy_ac, emac0_ptp, emac0_ptp, emac1_ptp, emac1_ptp, > + emac0_mcg0, _, _, _), > + [13] = PINGROUP(13, qup3_se0, emac0_mcg1, _, _, sail_top, _, _, _, _), > + [14] = PINGROUP(14, qup3_se0, emac0_mcg2, _, _, sail_top, _, _, _, _), > + [15] = PINGROUP(15, qup3_se0, emac0_mcg3, _, _, sail_top, _, _, _, _), > + [16] = PINGROUP(16, qup3_se0, emac1_mcg0, _, _, sail_top, _, _, _, _), > + [17] = PINGROUP(17, qup3_se0, tb_trig, tb_trig, emac1_mcg1, _, _, _, _, _), > + [18] = PINGROUP(18, qup3_se0, emac1_mcg2, _, _, sailss_ospi, sailss_emac0, _, _, _), > + [19] = PINGROUP(19, qup3_se0, emac1_mcg3, _, _, sailss_ospi, sailss_emac0, _, _, _), > + [20] = PINGROUP(20, qup0_se0, emac1_mdc, qdss_gpio, _, _, _, _, _, _), > + [21] = PINGROUP(21, qup0_se0, emac1_mdio, qdss_gpio, _, _, _, _, _, _), > + [22] = PINGROUP(22, qup0_se0, qdss_gpio15, _, _, _, _, _, _, _), > + [23] = PINGROUP(23, qup0_se0, qdss_gpio14, _, _, _, _, _, _, _), > + [24] = PINGROUP(24, qup0_se1, qdss_gpio13, _, _, _, _, _, _, _), > + [25] = PINGROUP(25, qup0_se1, phase_flag31, _, qdss_gpio12, _, _, _, _, _), > + [26] = PINGROUP(26, sgmii_phy, qup0_se1, qdss_cti, phase_flag30, _, _, _, _, _), > + [27] = PINGROUP(27, qup0_se1, qdss_cti, phase_flag29, _, atest_char, _, _, _, _), > + [28] = PINGROUP(28, qup0_se3, phase_flag28, _, qdss_gpio11, _, _, _, _, _), > + [29] = PINGROUP(29, qup0_se3, phase_flag27, _, qdss_gpio10, _, _, _, _, _), > + [30] = PINGROUP(30, qup0_se3, phase_flag26, _, qdss_gpio9, _, _, _, _, _), > + [31] = PINGROUP(31, qup0_se3, phase_flag25, _, qdss_gpio8, _, _, _, _, _), > + [32] = PINGROUP(32, qup0_se4, phase_flag24, _, _, _, _, _, _, _), > + [33] = PINGROUP(33, qup0_se4, gcc_gp4, _, ddr_pxi0, _, _, _, _, _), > + [34] = PINGROUP(34, qup0_se4, gcc_gp5, _, ddr_pxi0, _, _, _, _, _), > + [35] = PINGROUP(35, qup0_se4, phase_flag23, _, _, _, _, _, _, _), > + [36] = PINGROUP(36, qup0_se2, qup0_se5, phase_flag22, tgu_ch2, _, _, _, _, _), > + [37] = PINGROUP(37, qup0_se2, qup0_se5, phase_flag21, tgu_ch3, _, _, _, _, _), > + [38] = PINGROUP(38, qup0_se5, qup0_se2, qdss_cti, phase_flag20, tgu_ch4, _, _, _, _), > + [39] = PINGROUP(39, qup0_se5, qup0_se2, qdss_cti, phase_flag19, tgu_ch5, _, _, _, _), > + [40] = PINGROUP(40, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync0, _, _, _, _, _), > + [41] = PINGROUP(41, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync1, _, _, _, _, _), > + [42] = PINGROUP(42, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync2, gcc_gp5, _, _, _, _), > + [43] = PINGROUP(43, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync3, _, _, _, _, _), > + [44] = PINGROUP(44, qup1_se2, qup1_se3, edp0_lcd, _, _, _, _, _, _), > + [45] = PINGROUP(45, qup1_se2, qup1_se3, edp1_lcd, _, _, _, _, _, _), > + [46] = PINGROUP(46, qup1_se3, qup1_se2, mdp1_vsync4, tgu_ch0, _, _, _, _, _), > + [47] = PINGROUP(47, qup1_se3, qup1_se2, mdp1_vsync5, tgu_ch1, _, _, _, _, _), > + [48] = PINGROUP(48, qup1_se4, qdss_cti, edp2_lcd, _, _, _, _, _, _), > + [49] = PINGROUP(49, qup1_se4, qdss_cti, edp3_lcd, _, _, _, _, _, _), > + [50] = PINGROUP(50, qup1_se4, cci_async, qdss_cti, mdp1_vsync8, _, _, _, _, _), > + [51] = PINGROUP(51, qup1_se4, qdss_cti, mdp1_vsync6, gcc_gp1, _, _, _, _, _), > + [52] = PINGROUP(52, qup1_se5, cci_timer4, cci_i2c, mdp1_vsync7, gcc_gp2, _, ddr_pxi1, _, _), > + [53] = PINGROUP(53, qup1_se5, cci_timer5, cci_i2c, gcc_gp3, _, ddr_pxi1, _, _, _), > + [54] = PINGROUP(54, qup1_se5, cci_timer6, cci_i2c, _, _, _, _, _, _), > + [55] = PINGROUP(55, qup1_se5, cci_timer7, cci_i2c, gcc_gp4, _, ddr_pxi2, _, _, _), > + [56] = PINGROUP(56, qup1_se6, qup1_se6, cci_timer8, cci_i2c, phase_flag18, > + ddr_bist, _, _, _), > + [57] = PINGROUP(57, qup1_se6, qup1_se6, cci_timer9, cci_i2c, mdp0_vsync0, > + phase_flag17, ddr_bist, _, _), > + [58] = PINGROUP(58, cci_i2c, mdp0_vsync1, ddr_bist, _, atest_usb2, atest_char1, _, _, _), > + [59] = PINGROUP(59, cci_i2c, mdp0_vsync2, ddr_bist, _, atest_usb2, atest_char0, _, _, _), > + [60] = PINGROUP(60, cci_i2c, qdss_gpio0, _, _, _, _, _, _, _), > + [61] = PINGROUP(61, cci_i2c, qdss_gpio1, _, _, _, _, _, _, _), > + [62] = PINGROUP(62, cci_i2c, qdss_gpio2, _, _, _, _, _, _, _), > + [63] = PINGROUP(63, cci_i2c, qdss_gpio3, _, _, _, _, _, _, _), > + [64] = PINGROUP(64, cci_i2c, qdss_gpio4, _, _, _, _, _, _, _), > + [65] = PINGROUP(65, cci_i2c, qdss_gpio5, _, _, _, _, _, _, _), > + [66] = PINGROUP(66, cci_i2c, cci_async, qdss_gpio6, _, _, _, _, _, _), > + [67] = PINGROUP(67, cci_i2c, qdss_gpio7, _, _, _, _, _, _, _), > + [68] = PINGROUP(68, cci_timer0, cci_async, _, _, _, _, _, _, _), > + [69] = PINGROUP(69, cci_timer1, cci_async, _, _, _, _, _, _, _), > + [70] = PINGROUP(70, cci_timer2, cci_async, _, _, _, _, _, _, _), > + [71] = PINGROUP(71, cci_timer3, cci_async, _, _, _, _, _, _, _), > + [72] = PINGROUP(72, cam_mclk, _, _, _, _, _, _, _, _), > + [73] = PINGROUP(73, cam_mclk, _, _, _, _, _, _, _, _), > + [74] = PINGROUP(74, cam_mclk, _, _, _, _, _, _, _, _), > + [75] = PINGROUP(75, cam_mclk, _, _, _, _, _, _, _, _), > + [76] = PINGROUP(76, _, _, _, _, _, _, _, _, _), > + [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _), > + [78] = PINGROUP(78, _, _, _, _, _, _, _, _, _), > + [79] = PINGROUP(79, _, _, _, _, _, _, _, _, _), > + [80] = PINGROUP(80, qup2_se0, ibi_i3c, mdp0_vsync3, _, _, _, _, _, _), > + [81] = PINGROUP(81, qup2_se0, ibi_i3c, mdp0_vsync4, _, _, _, _, _, _), > + [82] = PINGROUP(82, qup2_se0, mdp_vsync, gcc_gp1, _, _, _, _, _, _), > + [83] = PINGROUP(83, qup2_se0, mdp_vsync, gcc_gp2, _, _, _, _, _, _), > + [84] = PINGROUP(84, qup2_se1, qup2_se5, ibi_i3c, mdp_vsync, gcc_gp3, _, _, _, _), > + [85] = PINGROUP(85, qup2_se1, qup2_se5, ibi_i3c, _, _, _, _, _, _), > + [86] = PINGROUP(86, qup2_se2, jitter_bist, atest_usb2, ddr_pxi2, _, _, _, _, _), > + [87] = PINGROUP(87, qup2_se2, pll_clk, atest_usb20, ddr_pxi3, _, _, _, _, _), > + [88] = PINGROUP(88, qup2_se2, _, atest_usb21, ddr_pxi3, _, _, _, _, _), > + [89] = PINGROUP(89, qup2_se2, _, atest_usb22, ddr_pxi4, atest_char3, _, _, _, _), > + [90] = PINGROUP(90, qup2_se2, _, atest_usb23, ddr_pxi4, atest_char2, _, _, _, _), > + [91] = PINGROUP(91, qup2_se3, mdp0_vsync5, _, atest_usb20, _, _, _, _, _), > + [92] = PINGROUP(92, qup2_se3, mdp0_vsync6, _, atest_usb21, _, _, _, _, _), > + [93] = PINGROUP(93, qup2_se3, mdp0_vsync7, _, atest_usb22, _, _, _, _, _), > + [94] = PINGROUP(94, qup2_se3, mdp0_vsync8, _, atest_usb23, _, _, _, _, _), > + [95] = PINGROUP(95, qup2_se4, qup2_se6, _, atest_usb20, _, _, _, _, _), > + [96] = PINGROUP(96, qup2_se4, qup2_se6, _, atest_usb21, _, _, _, _, _), > + [97] = PINGROUP(97, qup2_se6, qup2_se4, cri_trng0, _, atest_usb22, _, _, _, _), > + [98] = PINGROUP(98, qup2_se6, qup2_se4, phase_flag16, cri_trng1, _, _, _, _, _), > + [99] = PINGROUP(99, qup2_se5, qup2_se1, phase_flag15, cri_trng, _, _, _, _, _), > + [100] = PINGROUP(100, qup2_se5, qup2_se1, _, _, _, _, _, _, _), > + [101] = PINGROUP(101, edp0_hot, prng_rosc0, tsense_pwm4, _, _, _, _, _, _), > + [102] = PINGROUP(102, edp1_hot, prng_rosc1, tsense_pwm3, _, _, _, _, _, _), > + [103] = PINGROUP(103, edp3_hot, prng_rosc2, tsense_pwm2, _, _, _, _, _, _), > + [104] = PINGROUP(104, edp2_hot, prng_rosc3, tsense_pwm1, _, _, _, _, _, _), > + [105] = PINGROUP(105, mi2s_mclk0, _, qdss_gpio, atest_usb23, _, _, _, _, _), > + [106] = PINGROUP(106, mi2s1_sck, phase_flag14, _, qdss_gpio8, _, _, _, _, _), > + [107] = PINGROUP(107, mi2s1_ws, phase_flag13, _, qdss_gpio9, _, _, _, _, _), > + [108] = PINGROUP(108, mi2s1_data0, phase_flag12, _, qdss_gpio10, _, _, _, _, _), > + [109] = PINGROUP(109, mi2s1_data1, phase_flag11, _, qdss_gpio11, _, _, _, _, _), > + [110] = PINGROUP(110, mi2s2_sck, phase_flag10, _, qdss_gpio12, _, _, _, _, _), > + [111] = PINGROUP(111, mi2s2_ws, phase_flag9, _, qdss_gpio13, vsense_trigger, _, _, _, _), > + [112] = PINGROUP(112, mi2s2_data0, phase_flag8, _, qdss_gpio14, _, _, _, _, _), > + [113] = PINGROUP(113, mi2s2_data1, audio_ref, phase_flag7, _, qdss_gpio15, _, _, _, _), > + [114] = PINGROUP(114, hs0_mi2s, pll_bist, phase_flag6, _, qdss_gpio, _, _, _, _), > + [115] = PINGROUP(115, hs0_mi2s, _, qdss_gpio0, _, _, _, _, _, _), > + [116] = PINGROUP(116, hs0_mi2s, _, qdss_gpio1, _, _, _, _, _, _), > + [117] = PINGROUP(117, hs0_mi2s, mi2s_mclk1, _, qdss_gpio2, _, _, _, _, _), > + [118] = PINGROUP(118, hs1_mi2s, _, qdss_gpio3, ddr_pxi5, _, _, _, _, _), > + [119] = PINGROUP(119, hs1_mi2s, _, qdss_gpio4, ddr_pxi5, _, _, _, _, _), > + [120] = PINGROUP(120, hs1_mi2s, phase_flag5, _, qdss_gpio5, _, _, _, _, _), > + [121] = PINGROUP(121, hs1_mi2s, phase_flag4, _, qdss_gpio6, _, _, _, _, _), > + [122] = PINGROUP(122, hs2_mi2s, phase_flag3, _, qdss_gpio7, _, _, _, _, _), > + [123] = PINGROUP(123, hs2_mi2s, phase_flag2, _, _, _, _, _, _, _), > + [124] = PINGROUP(124, hs2_mi2s, phase_flag1, _, _, _, _, _, _, _), > + [125] = PINGROUP(125, hs2_mi2s, phase_flag0, _, _, _, _, _, _, _), > + [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _), > + [127] = PINGROUP(127, _, _, _, _, _, _, _, _, _), > + [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _), > + [129] = PINGROUP(129, _, _, _, _, _, _, _, _, _), > + [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _), > + [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _), > + [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _), > + [133] = PINGROUP(133, _, _, _, _, _, _, _, _, _), > + [134] = PINGROUP(134, _, _, _, _, _, _, _, _, _), > + [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _), > + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _), > + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _), > + [138] = PINGROUP(138, _, _, _, _, _, _, _, _, _), > + [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _), > + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _), > + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _), > + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _), > + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), > + [144] = PINGROUP(144, dbg_out, _, _, _, _, _, _, _, _), > + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _), > + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), > + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), > + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), > + [149] = UFS_RESET(ufs_reset, 0x1a2000), > + [150] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x199000, 15, 0), > + [151] = SDC_QDSD_PINGROUP(sdc1_clk, 0x199000, 13, 6), > + [152] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x199000, 11, 3), > + [153] = SDC_QDSD_PINGROUP(sdc1_data, 0x199000, 9, 0), > +}; > + > +static const struct msm_pinctrl_soc_data sa8775p_pinctrl = { > + .pins = sa8775p_pins, > + .npins = ARRAY_SIZE(sa8775p_pins), > + .functions = sa8775p_functions, > + .nfunctions = ARRAY_SIZE(sa8775p_functions), > + .groups = sa8775p_groups, > + .ngroups = ARRAY_SIZE(sa8775p_groups), > + .ngpios = 150, > +}; > + > +static int sa8775p_pinctrl_probe(struct platform_device *pdev) > +{ > + return msm_pinctrl_probe(pdev, &sa8775p_pinctrl); > +} > + > +static const struct of_device_id sa8775p_pinctrl_of_match[] = { > + { .compatible = "qcom,sa8775p-pinctrl", }, > + { }, > +}; > + > +static struct platform_driver sa8775p_pinctrl_driver = { > + .driver = { > + .name = "sa8775p-pinctrl", > + .of_match_table = sa8775p_pinctrl_of_match, > + }, > + .probe = sa8775p_pinctrl_probe, > + .remove = msm_pinctrl_remove, > +}; > + > +static int __init sa8775p_pinctrl_init(void) > +{ > + return platform_driver_register(&sa8775p_pinctrl_driver); > +} > +arch_initcall(sa8775p_pinctrl_init); > + > +static void __exit sa8775p_pinctrl_exit(void) > +{ > + platform_driver_unregister(&sa8775p_pinctrl_driver); > +} > +module_exit(sa8775p_pinctrl_exit); > + > +MODULE_DESCRIPTION("QTI SA8775P pinctrl driver"); > +MODULE_LICENSE("GPL"); > +MODULE_DEVICE_TABLE(of, sa8775p_pinctrl_of_match);
On 9.01.2023 18:45, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Add power domain description for sa8775p and a new compatible to match it. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > drivers/soc/qcom/rpmhpd.c | 34 ++++++++++++++++++++++++++++++++++ > 1 file changed, 34 insertions(+) > > diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c > index 4c2d2c296790..f20e2a49a669 100644 > --- a/drivers/soc/qcom/rpmhpd.c > +++ b/drivers/soc/qcom/rpmhpd.c > @@ -187,6 +187,16 @@ static struct rpmhpd nsp = { > .res_name = "nsp.lvl", > }; > > +static struct rpmhpd nsp0 = { > + .pd = { .name = "nsp0", }, > + .res_name = "nsp0.lvl", > +}; > + > +static struct rpmhpd nsp1 = { > + .pd = { .name = "nsp1", }, > + .res_name = "nsp1.lvl", > +}; > + > static struct rpmhpd qphy = { > .pd = { .name = "qphy", }, > .res_name = "qphy.lvl", > @@ -212,6 +222,29 @@ static const struct rpmhpd_desc sa8540p_desc = { > .num_pds = ARRAY_SIZE(sa8540p_rpmhpds), > }; > > +/* SA8775P RPMH power domains */ > +static struct rpmhpd *sa8775p_rpmhpds[] = { > + [SA8775P_CX] = &cx, > + [SA8775P_CX_AO] = &cx_ao, > + [SA8775P_EBI] = &ebi, > + [SA8775P_GFX] = &gfx, > + [SA8775P_LCX] = &lcx, > + [SA8775P_LMX] = &lmx, > + [SA8775P_MMCX] = &mmcx, > + [SA8775P_MMCX_AO] = &mmcx_ao, > + [SA8775P_MXC] = &mxc, > + [SA8775P_MXC_AO] = &mxc_ao, > + [SA8775P_MX] = &mx, > + [SA8775P_MX_AO] = &mx_ao, > + [SA8775P_NSP0] = &nsp0, > + [SA8775P_NSP1] = &nsp1, > +}; > + > +static const struct rpmhpd_desc sa8775p_desc = { > + .rpmhpds = sa8775p_rpmhpds, > + .num_pds = ARRAY_SIZE(sa8775p_rpmhpds), > +}; > + > /* SDM670 RPMH powerdomains */ > static struct rpmhpd *sdm670_rpmhpds[] = { > [SDM670_CX] = &cx_w_mx_parent, > @@ -487,6 +520,7 @@ static const struct rpmhpd_desc sc8280xp_desc = { > static const struct of_device_id rpmhpd_match_table[] = { > { .compatible = "qcom,qdu1000-rpmhpd", .data = &qdu1000_desc }, > { .compatible = "qcom,sa8540p-rpmhpd", .data = &sa8540p_desc }, > + { .compatible = "qcom,sa8775p-rpmhpd", .data = &sa8775p_desc }, > { .compatible = "qcom,sc7180-rpmhpd", .data = &sc7180_desc }, > { .compatible = "qcom,sc7280-rpmhpd", .data = &sc7280_desc }, > { .compatible = "qcom,sc8180x-rpmhpd", .data = &sc8180x_desc },
On 09/01/2023 18:45, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Add DT bindings for the TLMM controller on sa8775p platforms. Subject: drop second/last, redundant "bindings for". The "dt-bindings" prefix is already stating that these are bindings. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- > .../bindings/pinctrl/qcom,sa8775p-tlmm.yaml | 142 ++++++++++++++++++ > 1 file changed, 142 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml > new file mode 100644 > index 000000000000..44abf83b1358 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml > @@ -0,0 +1,142 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/qcom,sa8775p-tlmm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Technologies, Inc. SA8775P TLMM block > + > +maintainers: > + - Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > + > +description: | > + Top Level Mode Multiplexer pin controller in Qualcomm SA8775P SoC. > + > +allOf: > + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# > + > +properties: > + compatible: > + const: qcom,sa8775p-tlmm > + > + reg: > + maxItems: 1 > + > + interrupts: true > + interrupt-controller: true > + "#interrupt-cells": true > + gpio-controller: true > + "#gpio-cells": true > + gpio-ranges: true Add also gpio-reserved-ranges with min/maxItems (see for example sm8450) and gpio-line-names with maxItems. > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +patternProperties: > + "-state$": > + oneOf: > + - $ref: "#/$defs/qcom-sa8775p-tlmm-state" > + - patternProperties: > + "-pins$": > + $ref: "#/$defs/qcom-sa8775p-tlmm-state" > + additionalProperties: false > + > +$defs: > + qcom-sa8775p-tlmm-state: > + type: object > + description: > + Pinctrl node's client devices use subnodes for desired pin configuration. > + Client device subnodes use below standard properties. > + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state > + > + properties: > + pins: > + description: > + List of gpio pins affected by the properties specified in this > + subnode. > + items: > + oneOf: > + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$" > + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, ufs_reset ] Contents of this enum is sorted usually by name (not always, but we try for new bindings) > + minItems: 1 > + maxItems: 16 > + > + function: > + description: > + Specify the alternative function to be configured for the specified > + pins. > + > + enum: [ atest_char, atest_char0, atest_char1, atest_char2, > + atest_char3, atest_usb2, atest_usb20, atest_usb21, atest_usb22, > + atest_usb23, audio_ref, cam_mclk, cci_async, cci_i2c, > + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, > + cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9, > + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, > + ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, edp0_hot, > + edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot, > + edp3_lcd, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3, > + emac0_mdc, emac0_mdio, emac0_ptp, emac1_mcg0, emac1_mcg1, > + emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio, emac1_ptp, > + gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4, gcc_gp5, hs0_mi2s, hs1_mi2s, > + hs2_mi2s, ibi_i3c, jitter_bist, mdp0_vsync0, mdp0_vsync1, > + mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, > + mdp0_vsync7, mdp0_vsync8, mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, > + mdp1_vsync3, mdp1_vsync4, mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, > + mdp1_vsync8, mdp_vsync, mi2s1_data0, mi2s1_data1, mi2s1_sck, > + mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, > + mi2s_mclk0, mi2s_mclk1, pcie0_clkreq, pcie1_clkreq, phase_flag0, > + phase_flag1, phase_flag10, phase_flag11, phase_flag12, > + phase_flag13, phase_flag14, phase_flag15, phase_flag16, > + phase_flag17, phase_flag18, phase_flag19, phase_flag2, > + phase_flag20, phase_flag21, phase_flag22, phase_flag23, > + phase_flag24, phase_flag25, phase_flag26, phase_flag27, > + phase_flag28, phase_flag29, phase_flag3, phase_flag30, > + phase_flag31, phase_flag4, phase_flag5, phase_flag6, > + phase_flag7, phase_flag8, phase_flag9, pll_bist, pll_clk, > + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, > + qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, > + qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, qdss_gpio2, > + qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7, > + qdss_gpio8, qdss_gpio9, qup0_se0, qup0_se1, qup0_se2, qup0_se3, > + qup0_se4, qup0_se5, qup1_se0, qup1_se1, qup1_se2, qup1_se3, > + qup1_se4, qup1_se5, qup1_se6, qup2_se0, qup2_se1, qup2_se2, > + qup2_se3, qup2_se4, qup2_se5, qup2_se6, qup3_se0, sail_top, > + sailss_emac0, sailss_ospi, sgmii_phy, tb_trig, tgu_ch0, tgu_ch1, > + tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5, tsense_pwm1, tsense_pwm2, > + tsense_pwm3, tsense_pwm4, usb2phy_ac, vsense_trigger] Missing space before ] > + > + bias-disable: true > + bias-pull-down: true > + bias-pull-up: true > + drive-strength: true > + input-enable: true > + output-high: true > + output-low: true > + > + required: > + - pins > + > + additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + tlmm: pinctrl@f000000 { > + compatible = "qcom,sa8775p-pinctrl"; > + reg = <0xf000000 0x1000000>; > + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&tlmm 0 0 149>; Why only 149? > + > + qup_uart10_state { No underscores in node names.. which points to next one: Does not look like you tested the bindings. Please run `make dt_binding_check` (see Documentation/devicetree/bindings/writing-schema.rst for instructions). Best regards, Krzysztof
On 9.01.2023 18:58, Konrad Dybcio wrote: > > > On 9.01.2023 18:44, Bartosz Golaszewski wrote: >> From: Shazad Hussain <quic_shazhuss@quicinc.com> >> >> Add support for the Global Clock Controller found in the QTI SA8775P >> platforms. >> >> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> >> [Bartosz: made the driver ready for upstream] >> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >> --- > [...] > >> + >> +static struct gdsc usb20_prim_gdsc = { >> + .gdscr = 0x1C004, > Please use lowercase hex literals outside #defines. > >> + .pd = { >> + .name = "usb20_prim_gdsc", >> + }, >> + .pwrsts = PWRSTS_OFF_ON, >> +}; >> + > [...] > >> + >> +static const struct regmap_config gcc_sa8775p_regmap_config = { >> + .reg_bits = 32, >> + .reg_stride = 4, >> + .val_bits = 32, >> + .max_register = 0x472cffc, > This is faaaaar more than what your DT node specifies. > > With these two fixed, LGTM: > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > Konrad >> + .fast_io = true, >> +}; >> + >> +static const struct qcom_cc_desc gcc_sa8775p_desc = { >> + .config = &gcc_sa8775p_regmap_config, >> + .clks = gcc_sa8775p_clocks, >> + .num_clks = ARRAY_SIZE(gcc_sa8775p_clocks), >> + .resets = gcc_sa8775p_resets, >> + .num_resets = ARRAY_SIZE(gcc_sa8775p_resets), >> + .gdscs = gcc_sa8775p_gdscs, >> + .num_gdscs = ARRAY_SIZE(gcc_sa8775p_gdscs), >> +}; >> + >> +static const struct of_device_id gcc_sa8775p_match_table[] = { >> + { .compatible = "qcom,gcc-sa8775p" }, One more thing, this should be qcom,sa8775p-gcc. Konrad >> + { } >> +}; >> +MODULE_DEVICE_TABLE(of, gcc_sa8775p_match_table); >> + >> +static int gcc_sa8775p_probe(struct platform_device *pdev) >> +{ >> + struct regmap *regmap; >> + int ret; >> + >> + regmap = qcom_cc_map(pdev, &gcc_sa8775p_desc); >> + if (IS_ERR(regmap)) >> + return PTR_ERR(regmap); >> + >> + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, >> + ARRAY_SIZE(gcc_dfs_clocks)); >> + if (ret) >> + return ret; >> + >> + /* >> + * Keep the clocks always-ON >> + * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK, >> + * GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, >> + * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK. >> + */ >> + regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0)); >> + >> + return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); >> +} >> + >> +static struct platform_driver gcc_sa8775p_driver = { >> + .probe = gcc_sa8775p_probe, >> + .driver = { >> + .name = "gcc-sa8775p", >> + .of_match_table = gcc_sa8775p_match_table, >> + }, >> +}; >> + >> +static int __init gcc_sa8775p_init(void) >> +{ >> + return platform_driver_register(&gcc_sa8775p_driver); >> +} >> +subsys_initcall(gcc_sa8775p_init); >> + >> +static void __exit gcc_sa8775p_exit(void) >> +{ >> + platform_driver_unregister(&gcc_sa8775p_driver); >> +} >> +module_exit(gcc_sa8775p_exit); >> + >> +MODULE_DESCRIPTION("Qualcomm SA8775P GCC driver"); >> +MODULE_LICENSE("GPL");
On 09/01/2023 19:44, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > This adds basic support for the Qualcomm sa8775p platform and its reference > board: sa8775p-ride. The dtsi contains basic SoC description required for > a simple boot-to-shell. The dts enables boot-to-shell with UART on the > sa8775p-ride board. There are three new drivers required to boot the board: > pinctrl, interconnect and GCC clock. Other patches contain various tweaks > to existing code. More support is coming up. > > Bartosz Golaszewski (15): > dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p > arm64: defconfig: enable the clock driver for Qualcomm SA8775P > platforms > dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775p > clk: qcom: rpmh: add clocks for sa8775p > dt-bindings: interconnect: qcom: document the interconnects for > sa8775p > arm64: defconfig: enable the interconnect driver for Qualcomm SA8775P > dt-bindings: pinctrl: sa8775p: add bindings for qcom,sa8775p-tlmm > arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P > platforms > dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform > dt-bindings: power: qcom,rpmpd: document sa8775p > soc: qcom: rmphpd: add power domains for sa8775p > dt-bindings: arm-smmu: document the smmu on Qualcomm SA8775P > iommu: arm-smmu: qcom: add support for sa8775p > dt-bindings: arm: qcom: document the sa8775p reference board > arm64: dts: qcom: add initial support for qcom sa8775p-ride > > Shazad Hussain (2): > clk: qcom: add the GCC driver for sa8775p This patch didn't make it to the list. Please check if you can fix or split it somehow?
On 9.01.2023 21:13, Dmitry Baryshkov wrote: > On 09/01/2023 19:44, Bartosz Golaszewski wrote: >> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >> >> This adds basic support for the Qualcomm sa8775p platform and its reference >> board: sa8775p-ride. The dtsi contains basic SoC description required for >> a simple boot-to-shell. The dts enables boot-to-shell with UART on the >> sa8775p-ride board. There are three new drivers required to boot the board: >> pinctrl, interconnect and GCC clock. Other patches contain various tweaks >> to existing code. More support is coming up. >> >> Bartosz Golaszewski (15): >> dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p >> arm64: defconfig: enable the clock driver for Qualcomm SA8775P >> platforms >> dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775p >> clk: qcom: rpmh: add clocks for sa8775p >> dt-bindings: interconnect: qcom: document the interconnects for >> sa8775p >> arm64: defconfig: enable the interconnect driver for Qualcomm SA8775P >> dt-bindings: pinctrl: sa8775p: add bindings for qcom,sa8775p-tlmm >> arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P >> platforms >> dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform >> dt-bindings: power: qcom,rpmpd: document sa8775p >> soc: qcom: rmphpd: add power domains for sa8775p >> dt-bindings: arm-smmu: document the smmu on Qualcomm SA8775P >> iommu: arm-smmu: qcom: add support for sa8775p >> dt-bindings: arm: qcom: document the sa8775p reference board >> arm64: dts: qcom: add initial support for qcom sa8775p-ride >> >> Shazad Hussain (2): >> clk: qcom: add the GCC driver for sa8775p > > This patch didn't make it to the list. Please check if you can fix or split it somehow? It's a known issue with lists clipping messages that are too long. I'll forward it to you. Konrad >
On 09/01/2023 22:59, Konrad Dybcio wrote: > > > On 9.01.2023 21:13, Dmitry Baryshkov wrote: >> On 09/01/2023 19:44, Bartosz Golaszewski wrote: >>> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >>> >>> This adds basic support for the Qualcomm sa8775p platform and its reference >>> board: sa8775p-ride. The dtsi contains basic SoC description required for >>> a simple boot-to-shell. The dts enables boot-to-shell with UART on the >>> sa8775p-ride board. There are three new drivers required to boot the board: >>> pinctrl, interconnect and GCC clock. Other patches contain various tweaks >>> to existing code. More support is coming up. >>> >>> Bartosz Golaszewski (15): >>> dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p >>> arm64: defconfig: enable the clock driver for Qualcomm SA8775P >>> platforms >>> dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775p >>> clk: qcom: rpmh: add clocks for sa8775p >>> dt-bindings: interconnect: qcom: document the interconnects for >>> sa8775p >>> arm64: defconfig: enable the interconnect driver for Qualcomm SA8775P >>> dt-bindings: pinctrl: sa8775p: add bindings for qcom,sa8775p-tlmm >>> arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P >>> platforms >>> dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform >>> dt-bindings: power: qcom,rpmpd: document sa8775p >>> soc: qcom: rmphpd: add power domains for sa8775p >>> dt-bindings: arm-smmu: document the smmu on Qualcomm SA8775P >>> iommu: arm-smmu: qcom: add support for sa8775p >>> dt-bindings: arm: qcom: document the sa8775p reference board >>> arm64: dts: qcom: add initial support for qcom sa8775p-ride >>> >>> Shazad Hussain (2): >>> clk: qcom: add the GCC driver for sa8775p >> >> This patch didn't make it to the list. Please check if you can fix or split it somehow? > It's a known issue with lists clipping messages that are too long. > I'll forward it to you. Thank you!
On 09/01/2023 19:58, Konrad Dybcio wrote: > > > On 9.01.2023 18:44, Bartosz Golaszewski wrote: >> From: Shazad Hussain <quic_shazhuss@quicinc.com> >> >> Add support for the Global Clock Controller found in the QTI SA8775P >> platforms. >> >> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> >> [Bartosz: made the driver ready for upstream] >> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >> --- > [...] > As the driver didn't get to the list, I'll comment OOB. Please use clk_regmap_phy_mux_ops where applicable (PCIe PIPE clocks).
On Mon, 9 Jan 2023 18:44:53 +0100, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > This adds basic support for the Qualcomm sa8775p platform and its reference > board: sa8775p-ride. The dtsi contains basic SoC description required for > a simple boot-to-shell. The dts enables boot-to-shell with UART on the > sa8775p-ride board. There are three new drivers required to boot the board: > pinctrl, interconnect and GCC clock. Other patches contain various tweaks > to existing code. More support is coming up. > > [...] Applied, thanks! [13/18] dt-bindings: power: qcom,rpmpd: document sa8775p commit: b4f0370d3ce276397f5c48af99d0b77548825eb1 [14/18] soc: qcom: rmphpd: add power domains for sa8775p commit: 91e910adc59a6954e475dd2d6a4534ac56dd8eed Best regards,
On Mon, Jan 9, 2023 at 10:06 PM Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > On 09/01/2023 19:58, Konrad Dybcio wrote: > > > > > > On 9.01.2023 18:44, Bartosz Golaszewski wrote: > >> From: Shazad Hussain <quic_shazhuss@quicinc.com> > >> > >> Add support for the Global Clock Controller found in the QTI SA8775P > >> platforms. > >> > >> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> > >> [Bartosz: made the driver ready for upstream] > >> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > >> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > >> --- > > [...] > > > > As the driver didn't get to the list, I'll comment OOB. > > Please use clk_regmap_phy_mux_ops where applicable (PCIe PIPE clocks). > Looks like it's impossible for this platform as the PCIe PIPE clocks have two parents. Bart
On Tue, 17 Jan 2023 at 14:44, Bartosz Golaszewski <brgl@bgdev.pl> wrote: > > On Mon, Jan 9, 2023 at 10:06 PM Dmitry Baryshkov > <dmitry.baryshkov@linaro.org> wrote: > > > > On 09/01/2023 19:58, Konrad Dybcio wrote: > > > > > > > > > On 9.01.2023 18:44, Bartosz Golaszewski wrote: > > >> From: Shazad Hussain <quic_shazhuss@quicinc.com> > > >> > > >> Add support for the Global Clock Controller found in the QTI SA8775P > > >> platforms. > > >> > > >> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> > > >> [Bartosz: made the driver ready for upstream] > > >> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > >> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > >> --- > > > [...] > > > > > > > As the driver didn't get to the list, I'll comment OOB. > > > > Please use clk_regmap_phy_mux_ops where applicable (PCIe PIPE clocks). > > > > Looks like it's impossible for this platform as the PCIe PIPE clocks > have two parents. That's the point, please check the history of other platforms. XO becomes the 'off' state rather than being a separate parent.
On Mon, 9 Jan 2023 18:44:53 +0100, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > This adds basic support for the Qualcomm sa8775p platform and its reference > board: sa8775p-ride. The dtsi contains basic SoC description required for > a simple boot-to-shell. The dts enables boot-to-shell with UART on the > sa8775p-ride board. There are three new drivers required to boot the board: > pinctrl, interconnect and GCC clock. Other patches contain various tweaks > to existing code. More support is coming up. > > [...] Applied, thanks! [03/18] arm64: defconfig: enable the clock driver for Qualcomm SA8775P platforms commit: 1a87f7e5fa10b23633da03aed6b7c7e716457304 Best regards,
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> This adds basic support for the Qualcomm sa8775p platform and its reference board: sa8775p-ride. The dtsi contains basic SoC description required for a simple boot-to-shell. The dts enables boot-to-shell with UART on the sa8775p-ride board. There are three new drivers required to boot the board: pinctrl, interconnect and GCC clock. Other patches contain various tweaks to existing code. More support is coming up. Bartosz Golaszewski (15): dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p arm64: defconfig: enable the clock driver for Qualcomm SA8775P platforms dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775p clk: qcom: rpmh: add clocks for sa8775p dt-bindings: interconnect: qcom: document the interconnects for sa8775p arm64: defconfig: enable the interconnect driver for Qualcomm SA8775P dt-bindings: pinctrl: sa8775p: add bindings for qcom,sa8775p-tlmm arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P platforms dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform dt-bindings: power: qcom,rpmpd: document sa8775p soc: qcom: rmphpd: add power domains for sa8775p dt-bindings: arm-smmu: document the smmu on Qualcomm SA8775P iommu: arm-smmu: qcom: add support for sa8775p dt-bindings: arm: qcom: document the sa8775p reference board arm64: dts: qcom: add initial support for qcom sa8775p-ride Shazad Hussain (2): clk: qcom: add the GCC driver for sa8775p interconnect: qcom: add a driver for sa8775p Yadu MG (1): pinctrl: qcom: sa8775p: add the pinctrl driver for the sa8775p platform .../devicetree/bindings/arm/qcom.yaml | 5 + .../bindings/clock/qcom,gcc-sa8775p.yaml | 77 + .../bindings/clock/qcom,rpmhcc.yaml | 1 + .../bindings/interconnect/qcom,rpmh.yaml | 14 + .../devicetree/bindings/iommu/arm,smmu.yaml | 1 + .../bindings/mailbox/qcom-ipcc.yaml | 1 + .../bindings/pinctrl/qcom,sa8775p-tlmm.yaml | 142 + .../devicetree/bindings/power/qcom,rpmpd.yaml | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 39 + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 841 +++ arch/arm64/configs/defconfig | 3 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-rpmh.c | 17 + drivers/clk/qcom/gcc-sa8775p.c | 4806 +++++++++++++++++ drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/sa8775p.c | 2542 +++++++++ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sa8775p.c | 1649 ++++++ drivers/soc/qcom/rpmhpd.c | 34 + include/dt-bindings/clock/qcom,gcc-sa8775p.h | 320 ++ .../dt-bindings/interconnect/qcom,sa8775p.h | 231 + include/dt-bindings/power/qcom-rpmpd.h | 19 + 27 files changed, 10776 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi create mode 100644 drivers/clk/qcom/gcc-sa8775p.c create mode 100644 drivers/interconnect/qcom/sa8775p.c create mode 100644 drivers/pinctrl/qcom/pinctrl-sa8775p.c create mode 100644 include/dt-bindings/clock/qcom,gcc-sa8775p.h create mode 100644 include/dt-bindings/interconnect/qcom,sa8775p.h