From patchwork Wed Feb 1 11:35:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 13124176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5E5B8C636D3 for ; Wed, 1 Feb 2023 11:38:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=ENd6WjOJtyYsVYRkBj4UECllNaNP68FLwJurFNL6SLo=; b=5G1SoY3ie5IYYv coIfLCLVISLgzLmFNha6CdR73XqraorYVQaFe1h7NFGGnWA9lf4tScia97G7IqF/24PPNqAo+uPIe c4DLSJDN6IAHYKNVT9OXDfNNc2PJRdv/kTx3V29YDe6kMoK5WGMZWWTTwkBV4aC+PAkCHBaJ4CipH 1HcGCTfGxtwjoQZbNTT5Tf/UlBFkD+qiqzpnYXJE4tSDyjlv2WssMg2CdyXmorWOo9Qi8PSHG33DK JoIkcnQGp2j1ejx3KurAi3whGs4I4Ym18LIM6keRHEL5OvFjdiN3WRIpN/mHjS3YacWNIXzNoScW4 sFTJ5vdREmbZeg53QQGA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pNBQS-00BVfO-3z; Wed, 01 Feb 2023 11:37:16 +0000 Received: from relay10.mail.gandi.net ([217.70.178.230]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pNBPP-00BVFA-IU; Wed, 01 Feb 2023 11:36:15 +0000 Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id B6090240003; Wed, 1 Feb 2023 11:36:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1675251367; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=b0p8k1urwiI70DYegP0Had2KDZELpjVJ47Qs7x4Bvsc=; b=Ory6yMuw0b/2TWSppKfzQX8R3TyJFYPkwL9y0f7FK6ut1sNJK/I9s6NZD3XojWtHTDFf0e ZK0M6GrVKBfQ9PUFzdAiwPUB/X61d3iqXTLfGUdDKqqmZW+SObijtOlBuT1g1nnjZg3ujs yDHWIf4kv8LtXaUKV6rhzmuxfWFbHA8eppa4ONQUK51S0dcHokPsPCap2eioYfzlu4KT8l TDl32Ym4KutV8PW3YJ8HkCBYKgZS4UgnCDTUuAV9r8YadInJhf7MZ4IuASw+LB9CuO8coo covD2aHgW4zNOE47WrY9b/a+ayQ9wVW8BDiXkqJfxBr21o5RknqdYtZBodyhBA== From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: Julien Su , Jaime Liao , Jaime Liao , Alvin Zhou , Thomas Petazzoni , Michal Simek , , Miquel Raynal Subject: [PATCH v4 0/8] mtd: spi-nor: read while write support Date: Wed, 1 Feb 2023 12:35:55 +0100 Message-Id: <20230201113603.293758-1-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230201_033611_918294_A6E06C41 X-CRM114-Status: GOOD ( 31.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello folks, Here is the follow-up of the RFC trying to bring a little bit of parallelism to support SPI-NOR Read While Write feature on parts supporting it and featuring several banks. I have received some hardware to make it work, so since the RFC, the series has been updated to fix my mistakes, but the overall idea is the same. There is nothing Macronix specific in the implementation, the operations and opcodes are exactly the same as before. The only difference being: we may consider the chip usable when it is in the busy state during a write or an erase. Any chip with an internal split allowing to perform parallel operations might possibly leverage the benefits of this implementation. The first patches are just refactoring and preparation work, there is almost no functional change, it's just a way to prepare the introduction of the new locking mechanism and hopefully provide the cleanest and simplest diff possible for this new feature. The actual change is all contained in "mtd: spi-nor: Enhance locking to support reads while writes". The logic is described in the commit log and copy/pasted here for clarity: " On devices featuring several banks, the Read While Write (RWW) feature is here to improve the overall performance when performing parallel reads and writes at different locations (different banks). The following constraints have to be taken into account: 1#: A single operation can be performed in a given bank. 2#: Only a single program or erase operation can happen on the entire chip (common hardware limitation to limit costs) 3#: Reads must remain serialized even though reads on different banks might occur at the same time. 4#: The I/O bus is unique and thus is the most constrained resource, all spi-nor operations requiring access to the spi bus (through the spi controller) must be serialized until the bus exchanges are over. So we must ensure a single operation can be "sent" at a time. 5#: Any other operation that would not be either a read or a write or an erase is considered requiring access to the full chip and cannot be parallelized, we then need to ensure the full chip is in the idle state when this occurs. All these constraints can easily be managed with a proper locking model: 1#: Is enforced by a bitfield of the in-use banks, so that only a single operation can happen in a specific bank at any time. 2#: Is handled by the ongoing_pe boolean which is set before any write or erase, and is released only at the very end of the operation. This way, no other destructive operation on the chip can start during this time frame. 3#: An ongoing_rd boolean allows to track the ongoing reads, so that only one can be performed at a time. 4#: An ongoing_io boolean is introduced in order to capture and serialize bus accessed. This is the one being released "sooner" than before, because we only need to protect the chip against other SPI accesses during the I/O phase, which for the destructive operations is the beginning of the operation (when we send the command cycles and possibly the data), while the second part of the operation (the erase delay or the programmation delay) is when we can do something else in another bank. 5#: Is handled by the three booleans presented above, if any of them is set, the chip is not yet ready for the operation and must wait. All these internal variables are protected by the existing lock, so that changes in this structure are atomic. The serialization is handled with a wait queue." Here is now a benchmark with a Macronix MX25UW51245G with 4 banks and RWW support: // Testing the two accesses in the same bank $ flash_speed -b0 -k0 -c10 -d /dev/mtd0 [...] testing read while write latency read while write took 51ms, read ended after 51ms // Testing the two accesses within different banks $ flash_speed -b0 -k4096 -c10 -d /dev/mtd0 [...] testing read while write latency read while write took 51ms, read ended after 20ms Parallel accesses have been validated with io_paral. A slight increase of the time spent on this test has however been noticed. With my configuration, over a limited number of blocks, the overall operation took 22 min without any RWW changes up to 27 min with these changes, maybe due to the number of additional scheduling situations involved). Here is a branch with the mtd-utils patch bringing support for this additional "-k" parameter in flash_speed (for the second block to use during RWW testing), used to get the above results: https://github.com/miquelraynal/mtd-utils/compare/master...rww Cheers, Miquèl Changes in v4: * Dropped patch 1/9 which got applied. * s/SPI-NOR/SPI NOR/ * Turned n_banks into an u8 and moved it below in the struct to avoid padding. * Updated the S3AN_INFO macro to set n_banks to 1 by default. * Renamed the lock and prep helper to follow the order of each operation. * Reworded a commit log to fit the recent changes upstream. Changes in v3: * Fix the bank offsets calculations by providing the same values when locking and when unlocking (might be changed by the functions themselves without use noticing). * I completely changed the way the locking works because there was a new constraint: reads cannot be interrupted and status reads cannot happen during a read. Hence, as the multi-locks design was starting to be too messy, I changed the implementation to use a bunch of variables to track the read while write state, protected by the main spi-nor lock. If the internal state does not allow the operation, a sleep starts in a queue, until the threads are woken up after a state update. I know it is very verbose, I am open to suggestions. Miquel Raynal (8): mtd: spi-nor: Introduce the concept of bank mtd: spi-nor: Add a macro to define more banks mtd: spi-nor: Reorder the preparation vs locking steps mtd: spi-nor: Separate preparation and locking mtd: spi-nor: Prepare the introduction of a new locking mechanism mtd: spi-nor: Add a RWW flag mtd: spi-nor: Enhance locking to support reads while writes mtd: spi-nor: macronix: Add support for mx25uw51245g with RWW drivers/mtd/spi-nor/core.c | 396 +++++++++++++++++++++++++++++++-- drivers/mtd/spi-nor/core.h | 26 ++- drivers/mtd/spi-nor/macronix.c | 3 + drivers/mtd/spi-nor/xilinx.c | 1 + include/linux/mtd/spi-nor.h | 13 ++ 5 files changed, 409 insertions(+), 30 deletions(-)