From patchwork Sun Mar 19 16:07:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Oltmanns X-Patchwork-Id: 13180449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A75FFC6FD1F for ; Sun, 19 Mar 2023 16:08:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=mAVcolyklQsOio6K9hYU+2ZMbWcjnnWdY5G4ZnFUq9Q=; b=eh+RUJGgVKyk8a SQkrnwrR3OygWl3cS2n051DQDRd5hli6ObLQhm/bLLqw/WX3cfmz6LhfjYH0C/Kfjla5RaDEeunqc bboL2pDQ8rmrh5GB8d+Vhi84DVPQyU4FWvs/vVwYHx6Za2NpUhd+Yb9ns4qHUekE9CoQMHDad/8qU EMleKVcC17Z6ClaqjWw7xMbvFWzZq0POhXClfh4PFEGOWyTMda3vcQ3Qv6oKhLnblLJl6XtAhGin+ wMkQR5Of0XQcQg8O2Zc/wBo5JrbBHRxNYmpGVKqUxpJ4gB1wjjCUbxkWM+oAsIWy2ZS5sj78KFW29 gFAwgA7m1TBARR8TOlJg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pdvZJ-006zjX-1t; Sun, 19 Mar 2023 16:07:37 +0000 Received: from mout-p-202.mailbox.org ([80.241.56.172]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pdvZH-006zhz-0P for linux-arm-kernel@lists.infradead.org; Sun, 19 Mar 2023 16:07:36 +0000 Received: from smtp102.mailbox.org (smtp102.mailbox.org [10.196.197.102]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-202.mailbox.org (Postfix) with ESMTPS id 4PfjSG06Y0z9sSK; Sun, 19 Mar 2023 17:07:26 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oltmanns.dev; s=MBO0001; t=1679242046; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=LaQzIGUSIRQEvSeJYHlfv8DWhzz6rNivIcZxVXfH8Tk=; b=vbhGGBCRkeNdS0n2fuwDNEVBbNkJAYD154FDsqKO463PdmLfQgzvZR1LYH6aN0xzMSby9c ni5WA+LmVIJgHRVieSvleWvHc1fN6DGeMJxWjidXGDq3v1KiJDseE4Ld39tD0Ii0HExK/T yJmSPe6bTHRGPbh2umMycAJijEyV/mG428m+n3t/b/r1avxQp9D1OqkBYoHDw0sDI9K3P2 GfwqczV+J10oteeMi16xzK2mpTRkWrt3fTQsVOMbRcAb762IGS+/kyvuBHOi61BjRKGtCE 1A6ETN3C+BHVeJhmtwjBYK+ike5/AHE4cqkxR+IdJ2hQgKua7spVZ4DhhgisBA== From: Frank Oltmanns To: jagan@amarulasolutions.com, michael@amarulasolutions.com, Maxime Ripard , Chen-Yu Tsai , David Airlie , Daniel Vetter , Jernej Skrabec , Samuel Holland , dri-devel@lists.freedesktop.org (open list:DRM DRIVERS FOR ALLWINNER A10), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Allwinner sunXi SoC support), linux-sunxi@lists.linux.dev (open list:ARM/Allwinner sunXi SoC support), linux-kernel@vger.kernel.org (open list) Cc: Frank Oltmanns Subject: [PATCH 0/1] Fixing the DSI dot clock on Allwinner Date: Sun, 19 Mar 2023 17:07:03 +0100 Message-Id: <20230319160704.9858-1-frank@oltmanns.dev> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230319_090735_436409_C6BBDA78 X-CRM114-Status: GOOD ( 12.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org According to the Allwinner A64's BSP code, the PLL rate needs to be set to the following frequency when using DSI: PLL rate = DCLK * bpp / lanes Source: [1] The relevant lines for DSI (ommisions and comments mine): dclk_rate = lcdp->panel_info.lcd_dclk_freq * 1000000; lcd_rate = dclk_rate * clk_info.dsi_div; // dsi_div = bpp/lane pll_rate = lcd_rate * clk_info.lcd_div; // lcd_div = 1 --> pll_rate = lcd_rate dsi_rate = pll_rate / clk_info.dsi_div // --> dsi_rate = dclk_rate clk_set_rate(lcdp->clk_parent, pll_rate); This was already discussed by Maxime, Jagan and Michael in the past in the thread following this message: [2]. Unfortunately, there never was a conclusion in the form of code. The attached patch is a slight variation of a patch that is part of megi's kernel branch that many PinePhone distributions (e.g. postmarketOS) use [3]. It calculates the TCON clock rate by using the formula above and dividing it by SUN6I_DSI_TCON_DIV, in order to force the parent clock to be set to the correct rate. If I read the thread following this message [2] correctly, this was also what Maxime had in mind. Please also note that, unfortunately, I only have a single board and panel (namely the PinePhone) to test this on. Thanks, Frank [1] https://github.com/BPI-SINOVOIP/BPI-M64-bsp/blob/master/linux-sunxi/drivers/video/sunxi/disp2/disp/de/disp_lcd.c#L781 [2] https://lore.kernel.org/lkml/CAMty3ZAsH2iZ+JEqTE3D58aXfGuhMSg9YoO56ZhhOeE4c4yQHQ@mail.gmail.com/ [3] https://github.com/megous/linux/commit/eb5f28fb58727f4a6546f211486aad0d19cdea3f Frank Oltmanns (1): drm/sun4i: tcon: Fix setting PLL rate when using DSI drivers/gpu/drm/sun4i/sun4i_tcon.c | 46 ++++++++++++++++++++---------- 1 file changed, 31 insertions(+), 15 deletions(-)