[RFC,v2,0/2] irqchip: irq-ti-sci-inta: Add initial IRQ affinity support

Message

Vignesh Raghavendra March 27, 2023, 3:04 p.m. UTC

Interrupt Aggregator (INTA) IP INTA on TI's K3 SoCs convert DMA global
events (MSI like) to wired interrupts (VINT). 64 events can be mapped to
single VINT. Currently driver maps multiple events to single wired
interrupt line.  This makes setting IRQ affinity impossible as
migrating wired interrupt to different core will end up migrating all
events to that core.  And since DMA events related to networking IPs and
other high IRQ load IPs are behind this INTA logic, it creates load on a
single CPU, thus limiting overall performance of these peripherals

This series add ability to reserve have 1:1 mapping for certain events
(typically networking peripherals) using static soc specific data. These
VINTs are reserved at boot. IRQ affinity is handled at parent IRQ chip
(GIC or INTR - GIC).
This will provide consistent userspace irrespective of module
load/unload or probe order.

Based on discussions at [0]

Since RFC v1:
Rewrite patches to reserve few VINTs for direct mapping.

[0] v1:https://lore.kernel.org/linux-arm-kernel/[e-mail]/#r

---
Vignesh Raghavendra (2):
      irqchip: irq-ti-sci-inta: Allocates VINTs at probe
      irqchip: irq-ti-sci-inta: Add direct mapped interrupts

 drivers/irqchip/irq-ti-sci-inta.c | 289 +++++++---
 1 file changed, 212 insertions(+), 77 deletions(-)
---
base-commit: 011eb7443621f49ca1e8cdf9c74c215f25019118
change-id: 20230327-irq-affinity-upstream-a14c85a5e177

Best regards,