From patchwork Mon Mar 27 15:04:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 13189516 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A946EC76195 for ; Mon, 27 Mar 2023 15:05:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:CC:To:MIME-Version:Message-ID:Date: Subject:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=K9tl7Lva5HrlSGesDg0P+Fi9WOa8XwsI6Q399TAWla4=; b=AYyjVKnm8Zrb0i 7GWyRX1poQwnLFn4wbRkv6dbsWfNS40ShnB0ZzXwpeENRylCuMMmJfZgstb7F3QmnLZ/jL9h/WVbU +e3NaaFZ+reTe7uZxCIC6c+YKPsFE2RLUXyORL78EObrPIt+kYf2L3fzd30oqOhTT/sye/4tFvsMJ hr088UaXiWrWomIu/NlR/2D8xTAwDKQMDf6c6ouutvGAhMLZ2tkiSEAikGhv2AgEP3BPwctDfri9A JEEoEd+0j8PwF1bReSW15m0HqCODzmau2ojIZl8qTyDJ0ZNup3a8Hti7bzzYlXXZIdjqB8yLy0LbI XvsO6wtQnc6yo4ioWAvQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pgoP3-00BRKn-1O; Mon, 27 Mar 2023 15:04:57 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pgoP0-00BRHu-0k for linux-arm-kernel@lists.infradead.org; Mon, 27 Mar 2023 15:04:55 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32RF4YkC115278; Mon, 27 Mar 2023 10:04:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1679929474; bh=DLARxJLSXFtQS9cMddjuDaqL/7ZyzMy919eU9NUm9jg=; h=From:Subject:Date:To:CC; b=EazO9qv96Nla2O179AgnRgAuBjAYtDzQBwUs3DBf+ltrJ6/ArEAtNZdz7GdnNBHPI RG5KNOhapuwDUlKwxE/Z6g0hReQxcGVlg3Bq4pRrLQL5jWrmenOO9r0MOXgTS/eUTG ywm6krgLi4Qk4OJWRR/Z9TWVYY5Hpbx+kQQn7CFU= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32RF4YkP084766 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Mar 2023 10:04:34 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Mon, 27 Mar 2023 10:04:34 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Mon, 27 Mar 2023 10:04:33 -0500 Received: from [127.0.1.1] (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32RF4VTj080647; Mon, 27 Mar 2023 10:04:31 -0500 From: Vignesh Raghavendra Subject: [PATCH RFC v2 0/2] irqchip: irq-ti-sci-inta: Add initial IRQ affinity support Date: Mon, 27 Mar 2023 20:34:25 +0530 Message-ID: <20230327-irq-affinity-upstream-v2-0-1474e518f1cb@ti.com> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAHmwIWQC/23NQQ6CQAyF4auQrm0Cg2SMWxMP4NawKGNHunCEF g2GcHcH1y7/5H15CxirsMGxWED5LSbPlMPtCgg9pTuj3HKDK11d1s6j6IgUoySZPvgabFKmB1K 1D4eGGq68h2w7MsZOKYV+03/RthuUo8y//ytczido1/ULJGOAo5QAAAA= To: Nishanth Menon , Tero Kristo , Santosh Shilimkar , Thomas Gleixner , Marc Zyngier CC: , , Vignesh Raghavendra X-Mailer: b4 0.12.2 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230327_080454_363360_F32ECDC1 X-CRM114-Status: UNSURE ( 7.75 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Interrupt Aggregator (INTA) IP INTA on TI's K3 SoCs convert DMA global events (MSI like) to wired interrupts (VINT). 64 events can be mapped to single VINT. Currently driver maps multiple events to single wired interrupt line. This makes setting IRQ affinity impossible as migrating wired interrupt to different core will end up migrating all events to that core. And since DMA events related to networking IPs and other high IRQ load IPs are behind this INTA logic, it creates load on a single CPU, thus limiting overall performance of these peripherals This series add ability to reserve have 1:1 mapping for certain events (typically networking peripherals) using static soc specific data. These VINTs are reserved at boot. IRQ affinity is handled at parent IRQ chip (GIC or INTR - GIC). This will provide consistent userspace irrespective of module load/unload or probe order. Based on discussions at [0] Since RFC v1: Rewrite patches to reserve few VINTs for direct mapping. [0] v1:https://lore.kernel.org/linux-arm-kernel/20230122081607.959474-1-vigneshr@ti.com/#r --- Vignesh Raghavendra (2): irqchip: irq-ti-sci-inta: Allocates VINTs at probe irqchip: irq-ti-sci-inta: Add direct mapped interrupts drivers/irqchip/irq-ti-sci-inta.c | 289 +++++++--- 1 file changed, 212 insertions(+), 77 deletions(-) --- base-commit: 011eb7443621f49ca1e8cdf9c74c215f25019118 change-id: 20230327-irq-affinity-upstream-a14c85a5e177 Best regards,