From patchwork Wed Mar 29 15:39:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Marussi X-Patchwork-Id: 13192709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D67DC74A5B for ; Wed, 29 Mar 2023 15:40:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=NZVn4VuRw7Wj09qbW4SmxDYO20ZY9BaO6aTqZC/VNbA=; b=X0rYzvteUeBAhM 5H9dRI4snjlNC7BdcRO+aa2P5ocOm43Mu+CcR6+lbxJiCllrpSLbAOuFoSFd2qLDftYV7N1xN4OwI zj0OQGfb1PRWN6tASWqXnGI/+8wGRR+LjRTkqVpw2aLWtcF/DxPKQwBeCZrFNKf+85YsQ/nyM3N09 oqCgJEvVYAPIY+aJCKaxyWYQ9LBYS2Zh632C5eqn9LSLDXSkqHVTbBQa6OOgdSUECIxbznXijfOvG 1q1E0uYfcaetTZf9Bpnrfz68IiGreXv2QZAl1FjX4vowDxJYlRtK4StXYw+HPaEPiBgwULt4vAFE0 6SM4ZowHMGWBNnXm+AwQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1phXu1-000pKQ-0B; Wed, 29 Mar 2023 15:39:57 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1phXty-000pJ7-0I for linux-arm-kernel@lists.infradead.org; Wed, 29 Mar 2023 15:39:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C797E1FB; Wed, 29 Mar 2023 08:40:34 -0700 (PDT) Received: from e120937-lin.. (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1F0793F663; Wed, 29 Mar 2023 08:39:49 -0700 (PDT) From: Cristian Marussi To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: sudeep.holla@arm.com, cristian.marussi@arm.com, vincent.guittot@linaro.org, souvik.chakravarty@arm.com, nicola.mazzucato@arm.com, Tushar.Khandelwal@arm.com, viresh.kumar@linaro.org, jassisinghbrar@gmail.com Subject: [PATCH 0/2] Add MHUv2 support for multiple rx interrupt Date: Wed, 29 Mar 2023 16:39:34 +0100 Message-Id: <20230329153936.394911-1-cristian.marussi@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230329_083954_192936_0C801F04 X-CRM114-Status: GOOD ( 11.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, I was experimenting with a TotalCompute2022 (TC2) [1] reference design sporting MHUv2 (v2.x) mailboxes and running on top of it an SCMI stack configured platform-side to use multiple per-protocol channels with multiple rx interrupts but NOT using a combined interrupt. (it is not even wired at the hw-level on this platform anyway...) This configuration seemed not supported by the current driver which assumes that you have only one rx interrupt, possibly a combined one. Looking at the MHUv2 spec ([2]/[3] "Channels") seems indeed that per-channel rx-interrupts are indeed a possibility, beside the combined one. This small seriers aims to add such support by simply allowing to specify multiple rx interrupts in the DT node and taking care to register the same orginal ISR for all. On the tx path, instead, I left things unchanged and stuck with the current approach that just uses one single combined interrupt for the clear channel interrupt. (if supported at all) I tested on a TC2 model configured alternatively with MHU v2.1 and v2.0. Series based on v6.3-rc4. Any feedback welcome. Thanks, Cristian ---- [1]: https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/totalcompute/tc2/tc2_sw_stack.rst [2]: https://developer.arm.com/documentation/102342/0000/Message-Handling-Unit/About-the-Message-Handling-Unit/Channels?lang=en [3]: https://developer.arm.com/documentation/101418/0100/Message-Handling-Unit/Message-Handling-Unit-v2/Channel?lang=en Cristian Marussi (2): dt-bindings: mailbox : arm,mhuv2: Allow for more RX interrupts mailbox: arm_mhuv2: Add support for multiple rx interrupt .../bindings/mailbox/arm,mhuv2.yaml | 13 +++++--- drivers/mailbox/arm_mhuv2.c | 30 ++++++++++--------- 2 files changed, 25 insertions(+), 18 deletions(-)