[v5,00/17] drm/meson: add support for MIPI DSI Display

Message

Neil Armstrong May 30, 2023, 7:38 a.m. UTC

The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a),
with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI
glue on the same Amlogic SoCs.

This adds support for the glue managing the transceiver, mimicing the init flow provided
by Amlogic to setup the ENCL encoder, the glue, the transceiver, the digital D-PHY and the
Analog PHY in the proper way.

The DW-MIPI-DSI transceiver + D-PHY are clocked by the GP0 PLL, and the ENCL encoder + VIU
pixel reader by the VCLK2 clock using the HDMI PLL.

The DW-MIPI-DSI transceiver gets this pixel stream as input clocked with the VCLK2 clock.

An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
DW-MIPI-DSI transceiver.

This patchset is based on an earlier attempt at [1] for the AXG SoCs, but:
- previous glue code was a single monolitic code mixing encoders & bridges, this version
  is aligned on the previous cleanup done on HDMI & CVBS bridges architecture at [2]
- since the only output of AXG is DSI, AXG VPU support is post-poned until we implement
  single-clock DSI support specific case on top of this.

This is a re-spin of v3 at [5], the main change is about clock control, the clock
setup has been redesigned to use CCF, a common PLL (GP0) and the VCLK2 clock
path for DSI in preparation of full CCF support and possibly dual display with HDMI.

I kept review tags when the content was only slighly changed.

Signed-off-by: Neil Armstrong <[e-mail]>
---
Changes in v5:
- Aded PRIV all the G12 internal clk IDS to simplify public exposing
- Fixed the DSI bindings
- Fixed the DSI HSYNC/VSYNC polarity handling
- Fixed the DSI clock setup
- Fixed the DSI phy timings
- Dropped components for DSI, only keeping it for HDMI
- Added MNT Reform 2 CM4 DT
- Dropped already applied PHY fix
- Link to v4: https://lore.kernel.org/r/[e-mail]

Changes from v3 at [5]:
- switched all clk setup via CCF
- using single PLL for DSI controller & ENCL encoder
- added ENCL clocks to CCF
- make the VCLK2 clocks configuration by CCF
- fixed probe/bind of DSI controller to work with panels & bridges
- added bit_clk to controller to it can setup the BIT clock aswell
- added fix for components unbind
- added fix for analog phy setup value
- added TS050 timings fix
- dropped previous clk control patch

Changes from v2 at [4]:
- Fixed patch 3
- Added reviews from Jagan
- Rebased on v5.19-rc1

Changes from v1 at [3]:
- fixed DSI host bindings
- add reviewed-by tags for bindings
- moved magic values to defines thanks to Martin's searches
- added proper prefixes to defines
- moved phy_configure to phy_init() dw-mipi-dsi callback
- moved phy_on to a new phy_power_on() dw-mipi-dsi callback
- correctly return phy_init/configure errors to callback returns

[1] https://lore.kernel.org/r/[e-mail]
[2] https://lore.kernel.org/r/[e-mail]
[3] https://lore.kernel.org/r/[e-mail]
[4] https://lore.kernel.org/r/[e-mail]
[5] https://lore.kernel.org/r/[e-mail]

---
Neil Armstrong (17):
      clk: meson: g12a: prefix private CLK IDs defines with PRIV
      clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks
      dt-bindings: clk: g12a-clkc: add VCLK2_SEL and CTS_ENCL clock ids
      clk: meson: g12: use VCLK2_SEL, CTS_ENCL & CTS_ENCL_SEL public CLK IDs
      clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF
      dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings
      dt-bindings: display: meson-vpu: add third DPI output port
      drm/meson: fix unbind path if HDMI fails to bind
      drm/meson: only use components with dw-hdmi
      drm/meson: venc: add ENCL encoder setup for MIPI-DSI output
      drm/meson: add DSI encoder
      drm/meson: add support for MIPI-DSI transceiver
      drm/panel: khadas-ts050: update timings to achieve 60Hz refresh rate
      arm64: meson: g12-common: add the MIPI DSI nodes
      DONOTMERGE: arm64: meson: khadas-vim3l: add DSI panel
      dt-bindings: arm: amlogic: Document the MNT Reform 2 CM4 adapter with a BPI-CM4 Module
      arm64: dts: amlogic: meson-g12b-bananapi-cm4: add support for MNT Reform2 with CM4 adaper

 Documentation/devicetree/bindings/arm/amlogic.yaml |   1 +
 .../display/amlogic,meson-g12a-dw-mipi-dsi.yaml    | 118 +++
 .../bindings/display/amlogic,meson-vpu.yaml        |   5 +
 arch/arm64/boot/dts/amlogic/Makefile               |   1 +
 arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi  |  70 ++
 .../meson-g12b-bananapi-cm4-mnt-reform2.dts        | 388 ++++++++++
 .../boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi   |   2 +-
 arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi |  76 ++
 .../boot/dts/amlogic/meson-sm1-khadas-vim3l.dts    |   2 +-
 drivers/clk/meson/g12a.c                           | 791 ++++++++++++---------
 drivers/clk/meson/g12a.h                           | 261 ++++---
 drivers/gpu/drm/meson/Kconfig                      |   7 +
 drivers/gpu/drm/meson/Makefile                     |   3 +-
 drivers/gpu/drm/meson/meson_drv.c                  |  62 +-
 drivers/gpu/drm/meson/meson_drv.h                  |   1 +
 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c          | 352 +++++++++
 drivers/gpu/drm/meson/meson_dw_mipi_dsi.h          | 160 +++++
 drivers/gpu/drm/meson/meson_encoder_dsi.c          | 174 +++++
 drivers/gpu/drm/meson/meson_encoder_dsi.h          |  13 +
 drivers/gpu/drm/meson/meson_registers.h            |  25 +
 drivers/gpu/drm/meson/meson_venc.c                 | 211 +++++-
 drivers/gpu/drm/meson/meson_venc.h                 |   6 +
 drivers/gpu/drm/meson/meson_vpp.h                  |   2 +
 drivers/gpu/drm/panel/panel-khadas-ts050.c         |  16 +-
 include/dt-bindings/clock/g12a-clkc.h              |   3 +
 25 files changed, 2262 insertions(+), 488 deletions(-)
---
base-commit: 8c33787278ca8db73ad7d23f932c8c39b9f6e543
change-id: 20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-b8e5217e1f4a

Best regards,

Comments

Jerome Brunet May 30, 2023, 8:08 a.m. UTC | #1

On Tue 30 May 2023 at 09:38, Neil Armstrong <[e-mail]> wrote:

> Exposing should not be done in a single commit anymore due to
> dt-bindings enforced rules.
>
> Prepend PRIV to the private CLK IDs so we can add new clock to
> the bindings header and in a separate commit remove such private
> define and switch to the public CLK IDs identifier.
>
> This refers to a discussion at [1] with Arnd and Krzysztof.
>
> [1] https://lore.kernel.org/all/[e-mail]/
>
> Signed-off-by: Neil Armstrong <[e-mail]>

I understand the discussion reported but I don't really like this CLKID_PRIV_ 
It adds another layer of IDs.

I'd much prefer if we just expose all the IDs. That would comply with DT
new policy and be much simpler in the long run.

> ---
>  drivers/clk/meson/g12a.c | 628 +++++++++++++++++++++++------------------------
>  drivers/clk/meson/g12a.h | 260 ++++++++++----------
>  2 files changed, 444 insertions(+), 444 deletions(-)
>
> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
> index 310accf94830..d2e481ae2429 100644
> --- a/drivers/clk/meson/g12a.c
> +++ b/drivers/clk/meson/g12a.c
> @@ -4255,8 +4255,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
>  		[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
>  		[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
>  		[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
> -		[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
> -		[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
> +		[CLKID_PRIV_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
> +		[CLKID_PRIV_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>  		[CLKID_CLK81]			= &g12a_clk81.hw,
>  		[CLKID_MPLL0]			= &g12a_mpll0.hw,
>  		[CLKID_MPLL1]			= &g12a_mpll1.hw,
> @@ -4307,25 +4307,25 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
>  		[CLKID_UART2]			= &g12a_uart2.hw,
>  		[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
>  		[CLKID_GIC]			= &g12a_gic.hw,
> -		[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
> -		[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
> +		[CLKID_PRIV_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
> +		[CLKID_PRIV_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>  		[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
> -		[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
> -		[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
> +		[CLKID_PRIV_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
> +		[CLKID_PRIV_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>  		[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
> -		[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
> -		[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
> +		[CLKID_PRIV_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
> +		[CLKID_PRIV_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>  		[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
> -		[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
> -		[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
> -		[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
> -		[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
> -		[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
> -		[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
> -		[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
> -		[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
> -		[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
> -		[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
> +		[CLKID_PRIV_MPLL0_DIV]		= &g12a_mpll0_div.hw,
> +		[CLKID_PRIV_MPLL1_DIV]		= &g12a_mpll1_div.hw,
> +		[CLKID_PRIV_MPLL2_DIV]		= &g12a_mpll2_div.hw,
> +		[CLKID_PRIV_MPLL3_DIV]		= &g12a_mpll3_div.hw,
> +		[CLKID_PRIV_FCLK_DIV2_DIV]	= &g12a_fclk_div2_div.hw,
> +		[CLKID_PRIV_FCLK_DIV3_DIV]	= &g12a_fclk_div3_div.hw,
> +		[CLKID_PRIV_FCLK_DIV4_DIV]	= &g12a_fclk_div4_div.hw,
> +		[CLKID_PRIV_FCLK_DIV5_DIV]	= &g12a_fclk_div5_div.hw,
> +		[CLKID_PRIV_FCLK_DIV7_DIV]	= &g12a_fclk_div7_div.hw,
> +		[CLKID_PRIV_FCLK_DIV2P5_DIV]	= &g12a_fclk_div2p5_div.hw,
>  		[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
>  		[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
>  		[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
> @@ -4346,56 +4346,56 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
>  		[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
>  		[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
>  		[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
> -		[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
> -		[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
> -		[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
> -		[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
> +		[CLKID_PRIV_FIXED_PLL_DCO]	= &g12a_fixed_pll_dco.hw,
> +		[CLKID_PRIV_SYS_PLL_DCO]	= &g12a_sys_pll_dco.hw,
> +		[CLKID_PRIV_GP0_PLL_DCO]	= &g12a_gp0_pll_dco.hw,
> +		[CLKID_PRIV_HIFI_PLL_DCO]	= &g12a_hifi_pll_dco.hw,
>  		[CLKID_DMA]			= &g12a_dma.hw,
>  		[CLKID_EFUSE]			= &g12a_efuse.hw,
>  		[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
>  		[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
>  		[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
> -		[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
> +		[CLKID_PRIV_MPLL_PREDIV]	= &g12a_mpll_prediv.hw,
>  		[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
> -		[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
> +		[CLKID_PRIV_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>  		[CLKID_VPU_0]			= &g12a_vpu_0.hw,
>  		[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
> -		[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
> +		[CLKID_PRIV_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>  		[CLKID_VPU_1]			= &g12a_vpu_1.hw,
>  		[CLKID_VPU]			= &g12a_vpu.hw,
>  		[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
> -		[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
> +		[CLKID_PRIV_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>  		[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
>  		[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
> -		[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
> +		[CLKID_PRIV_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>  		[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
>  		[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
>  		[CLKID_VAPB]			= &g12a_vapb.hw,
> -		[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
> -		[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
> -		[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
> +		[CLKID_PRIV_HDMI_PLL_DCO]	= &g12a_hdmi_pll_dco.hw,
> +		[CLKID_PRIV_HDMI_PLL_OD]	= &g12a_hdmi_pll_od.hw,
> +		[CLKID_PRIV_HDMI_PLL_OD2]	= &g12a_hdmi_pll_od2.hw,
>  		[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
>  		[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
> -		[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
> -		[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
> -		[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
> -		[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
> -		[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
> -		[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
> -		[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
> -		[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
> +		[CLKID_PRIV_VID_PLL_SEL]	= &g12a_vid_pll_sel.hw,
> +		[CLKID_PRIV_VID_PLL_DIV]	= &g12a_vid_pll.hw,
> +		[CLKID_PRIV_VCLK_SEL]		= &g12a_vclk_sel.hw,
> +		[CLKID_PRIV_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
> +		[CLKID_PRIV_VCLK_INPUT]		= &g12a_vclk_input.hw,
> +		[CLKID_PRIV_VCLK2_INPUT]	= &g12a_vclk2_input.hw,
> +		[CLKID_PRIV_VCLK_DIV]		= &g12a_vclk_div.hw,
> +		[CLKID_PRIV_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>  		[CLKID_VCLK]			= &g12a_vclk.hw,
>  		[CLKID_VCLK2]			= &g12a_vclk2.hw,
>  		[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
> -		[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
> -		[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
> -		[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
> -		[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
> +		[CLKID_PRIV_VCLK_DIV2_EN]	= &g12a_vclk_div2_en.hw,
> +		[CLKID_PRIV_VCLK_DIV4_EN]	= &g12a_vclk_div4_en.hw,
> +		[CLKID_PRIV_VCLK_DIV6_EN]	= &g12a_vclk_div6_en.hw,
> +		[CLKID_PRIV_VCLK_DIV12_EN]	= &g12a_vclk_div12_en.hw,
>  		[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
> -		[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
> -		[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
> -		[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
> -		[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
> +		[CLKID_PRIV_VCLK2_DIV2_EN]	= &g12a_vclk2_div2_en.hw,
> +		[CLKID_PRIV_VCLK2_DIV4_EN]	= &g12a_vclk2_div4_en.hw,
> +		[CLKID_PRIV_VCLK2_DIV6_EN]	= &g12a_vclk2_div6_en.hw,
> +		[CLKID_PRIV_VCLK2_DIV12_EN]	= &g12a_vclk2_div12_en.hw,
>  		[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
>  		[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
>  		[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
> @@ -4404,69 +4404,69 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
>  		[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
>  		[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
>  		[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
> -		[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
> -		[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
> -		[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
> -		[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
> +		[CLKID_PRIV_CTS_ENCI_SEL]	= &g12a_cts_enci_sel.hw,
> +		[CLKID_PRIV_CTS_ENCP_SEL]	= &g12a_cts_encp_sel.hw,
> +		[CLKID_PRIV_CTS_VDAC_SEL]	= &g12a_cts_vdac_sel.hw,
> +		[CLKID_PRIV_HDMI_TX_SEL]	= &g12a_hdmi_tx_sel.hw,
>  		[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
>  		[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
>  		[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
>  		[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
> -		[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
> -		[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
> +		[CLKID_PRIV_HDMI_SEL]		= &g12a_hdmi_sel.hw,
> +		[CLKID_PRIV_HDMI_DIV]		= &g12a_hdmi_div.hw,
>  		[CLKID_HDMI]			= &g12a_hdmi.hw,
>  		[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
> -		[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
> +		[CLKID_PRIV_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>  		[CLKID_MALI_0]			= &g12a_mali_0.hw,
>  		[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
> -		[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
> +		[CLKID_PRIV_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>  		[CLKID_MALI_1]			= &g12a_mali_1.hw,
>  		[CLKID_MALI]			= &g12a_mali.hw,
> -		[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
> +		[CLKID_PRIV_MPLL_50M_DIV]	= &g12a_mpll_50m_div.hw,
>  		[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
> -		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
> -		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
> -		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
> -		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
> -		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
> -		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
> -		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
> -		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
> -		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
> +		[CLKID_PRIV_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
> +		[CLKID_PRIV_SYS_PLL_DIV16]	= &g12a_sys_pll_div16.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN0]	= &g12a_cpu_clk_postmux0.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN1]	= &g12a_cpu_clk_postmux1.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN]	= &g12a_cpu_clk_dyn.hw,
>  		[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,
> -		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
> -		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
> -		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
> -		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
> -		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
> -		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
> -		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
> -		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
> -		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
> -		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
> -		[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
> -		[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
> -		[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
> +		[CLKID_PRIV_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
> +		[CLKID_PRIV_CPU_CLK_DIV16]	= &g12a_cpu_clk_div16.hw,
> +		[CLKID_PRIV_CPU_CLK_APB_DIV]	= &g12a_cpu_clk_apb_div.hw,
> +		[CLKID_PRIV_CPU_CLK_APB]	= &g12a_cpu_clk_apb.hw,
> +		[CLKID_PRIV_CPU_CLK_ATB_DIV]	= &g12a_cpu_clk_atb_div.hw,
> +		[CLKID_PRIV_CPU_CLK_ATB]	= &g12a_cpu_clk_atb.hw,
> +		[CLKID_PRIV_CPU_CLK_AXI_DIV]	= &g12a_cpu_clk_axi_div.hw,
> +		[CLKID_PRIV_CPU_CLK_AXI]	= &g12a_cpu_clk_axi.hw,
> +		[CLKID_PRIV_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
> +		[CLKID_PRIV_CPU_CLK_TRACE]	= &g12a_cpu_clk_trace.hw,
> +		[CLKID_PRIV_PCIE_PLL_DCO]	= &g12a_pcie_pll_dco.hw,
> +		[CLKID_PRIV_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
> +		[CLKID_PRIV_PCIE_PLL_OD]	= &g12a_pcie_pll_od.hw,
>  		[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
> -		[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
> -		[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
> +		[CLKID_PRIV_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
> +		[CLKID_PRIV_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>  		[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
> -		[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
> -		[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
> +		[CLKID_PRIV_VDEC_HEVC_SEL]	= &g12a_vdec_hevc_sel.hw,
> +		[CLKID_PRIV_VDEC_HEVC_DIV]	= &g12a_vdec_hevc_div.hw,
>  		[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
> -		[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
> -		[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
> +		[CLKID_PRIV_VDEC_HEVCF_SEL]	= &g12a_vdec_hevcf_sel.hw,
> +		[CLKID_PRIV_VDEC_HEVCF_DIV]	= &g12a_vdec_hevcf_div.hw,
>  		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
> -		[CLKID_TS_DIV]			= &g12a_ts_div.hw,
> +		[CLKID_PRIV_TS_DIV]		= &g12a_ts_div.hw,
>  		[CLKID_TS]			= &g12a_ts.hw,
> -		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
> -		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
> +		[CLKID_PRIV_SPICC0_SCLK_SEL]	= &g12a_spicc0_sclk_sel.hw,
> +		[CLKID_PRIV_SPICC0_SCLK_DIV]	= &g12a_spicc0_sclk_div.hw,
>  		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
> -		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
> -		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
> +		[CLKID_PRIV_SPICC1_SCLK_SEL]	= &g12a_spicc1_sclk_sel.hw,
> +		[CLKID_PRIV_SPICC1_SCLK_DIV]	= &g12a_spicc1_sclk_div.hw,
>  		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
>  		[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
> -		[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
> +		[CLKID_PRIV_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>  		[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
>  		[NR_CLKS]			= NULL,
>  	},
> @@ -4484,8 +4484,8 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
>  		[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
>  		[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
>  		[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
> -		[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
> -		[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
> +		[CLKID_PRIV_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
> +		[CLKID_PRIV_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>  		[CLKID_CLK81]			= &g12a_clk81.hw,
>  		[CLKID_MPLL0]			= &g12a_mpll0.hw,
>  		[CLKID_MPLL1]			= &g12a_mpll1.hw,
> @@ -4536,25 +4536,25 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
>  		[CLKID_UART2]			= &g12a_uart2.hw,
>  		[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
>  		[CLKID_GIC]			= &g12a_gic.hw,
> -		[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
> -		[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
> +		[CLKID_PRIV_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
> +		[CLKID_PRIV_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>  		[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
> -		[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
> -		[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
> +		[CLKID_PRIV_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
> +		[CLKID_PRIV_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>  		[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
> -		[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
> -		[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
> +		[CLKID_PRIV_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
> +		[CLKID_PRIV_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>  		[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
> -		[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
> -		[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
> -		[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
> -		[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
> -		[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
> -		[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
> -		[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
> -		[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
> -		[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
> -		[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
> +		[CLKID_PRIV_MPLL0_DIV]		= &g12a_mpll0_div.hw,
> +		[CLKID_PRIV_MPLL1_DIV]		= &g12a_mpll1_div.hw,
> +		[CLKID_PRIV_MPLL2_DIV]		= &g12a_mpll2_div.hw,
> +		[CLKID_PRIV_MPLL3_DIV]		= &g12a_mpll3_div.hw,
> +		[CLKID_PRIV_FCLK_DIV2_DIV]	= &g12a_fclk_div2_div.hw,
> +		[CLKID_PRIV_FCLK_DIV3_DIV]	= &g12a_fclk_div3_div.hw,
> +		[CLKID_PRIV_FCLK_DIV4_DIV]	= &g12a_fclk_div4_div.hw,
> +		[CLKID_PRIV_FCLK_DIV5_DIV]	= &g12a_fclk_div5_div.hw,
> +		[CLKID_PRIV_FCLK_DIV7_DIV]	= &g12a_fclk_div7_div.hw,
> +		[CLKID_PRIV_FCLK_DIV2P5_DIV]	= &g12a_fclk_div2p5_div.hw,
>  		[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
>  		[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
>  		[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
> @@ -4575,56 +4575,56 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
>  		[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
>  		[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
>  		[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
> -		[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
> -		[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
> -		[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
> -		[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
> +		[CLKID_PRIV_FIXED_PLL_DCO]	= &g12a_fixed_pll_dco.hw,
> +		[CLKID_PRIV_SYS_PLL_DCO]	= &g12a_sys_pll_dco.hw,
> +		[CLKID_PRIV_GP0_PLL_DCO]	= &g12a_gp0_pll_dco.hw,
> +		[CLKID_PRIV_HIFI_PLL_DCO]	= &g12a_hifi_pll_dco.hw,
>  		[CLKID_DMA]			= &g12a_dma.hw,
>  		[CLKID_EFUSE]			= &g12a_efuse.hw,
>  		[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
>  		[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
>  		[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
> -		[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
> +		[CLKID_PRIV_MPLL_PREDIV]	= &g12a_mpll_prediv.hw,
>  		[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
> -		[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
> +		[CLKID_PRIV_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>  		[CLKID_VPU_0]			= &g12a_vpu_0.hw,
>  		[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
> -		[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
> +		[CLKID_PRIV_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>  		[CLKID_VPU_1]			= &g12a_vpu_1.hw,
>  		[CLKID_VPU]			= &g12a_vpu.hw,
>  		[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
> -		[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
> +		[CLKID_PRIV_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>  		[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
>  		[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
> -		[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
> +		[CLKID_PRIV_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>  		[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
>  		[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
>  		[CLKID_VAPB]			= &g12a_vapb.hw,
> -		[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
> -		[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
> -		[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
> +		[CLKID_PRIV_HDMI_PLL_DCO]	= &g12a_hdmi_pll_dco.hw,
> +		[CLKID_PRIV_HDMI_PLL_OD]	= &g12a_hdmi_pll_od.hw,
> +		[CLKID_PRIV_HDMI_PLL_OD2]	= &g12a_hdmi_pll_od2.hw,
>  		[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
>  		[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
> -		[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
> -		[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
> -		[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
> -		[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
> -		[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
> -		[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
> -		[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
> -		[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
> +		[CLKID_PRIV_VID_PLL_SEL]	= &g12a_vid_pll_sel.hw,
> +		[CLKID_PRIV_VID_PLL_DIV]	= &g12a_vid_pll.hw,
> +		[CLKID_PRIV_VCLK_SEL]		= &g12a_vclk_sel.hw,
> +		[CLKID_PRIV_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
> +		[CLKID_PRIV_VCLK_INPUT]		= &g12a_vclk_input.hw,
> +		[CLKID_PRIV_VCLK2_INPUT]	= &g12a_vclk2_input.hw,
> +		[CLKID_PRIV_VCLK_DIV]		= &g12a_vclk_div.hw,
> +		[CLKID_PRIV_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>  		[CLKID_VCLK]			= &g12a_vclk.hw,
>  		[CLKID_VCLK2]			= &g12a_vclk2.hw,
>  		[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
> -		[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
> -		[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
> -		[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
> -		[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
> +		[CLKID_PRIV_VCLK_DIV2_EN]	= &g12a_vclk_div2_en.hw,
> +		[CLKID_PRIV_VCLK_DIV4_EN]	= &g12a_vclk_div4_en.hw,
> +		[CLKID_PRIV_VCLK_DIV6_EN]	= &g12a_vclk_div6_en.hw,
> +		[CLKID_PRIV_VCLK_DIV12_EN]	= &g12a_vclk_div12_en.hw,
>  		[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
> -		[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
> -		[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
> -		[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
> -		[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
> +		[CLKID_PRIV_VCLK2_DIV2_EN]	= &g12a_vclk2_div2_en.hw,
> +		[CLKID_PRIV_VCLK2_DIV4_EN]	= &g12a_vclk2_div4_en.hw,
> +		[CLKID_PRIV_VCLK2_DIV6_EN]	= &g12a_vclk2_div6_en.hw,
> +		[CLKID_PRIV_VCLK2_DIV12_EN]	= &g12a_vclk2_div12_en.hw,
>  		[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
>  		[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
>  		[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
> @@ -4633,104 +4633,104 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
>  		[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
>  		[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
>  		[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
> -		[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
> -		[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
> -		[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
> -		[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
> +		[CLKID_PRIV_CTS_ENCI_SEL]	= &g12a_cts_enci_sel.hw,
> +		[CLKID_PRIV_CTS_ENCP_SEL]	= &g12a_cts_encp_sel.hw,
> +		[CLKID_PRIV_CTS_VDAC_SEL]	= &g12a_cts_vdac_sel.hw,
> +		[CLKID_PRIV_HDMI_TX_SEL]	= &g12a_hdmi_tx_sel.hw,
>  		[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
>  		[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
>  		[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
>  		[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
> -		[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
> -		[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
> +		[CLKID_PRIV_HDMI_SEL]		= &g12a_hdmi_sel.hw,
> +		[CLKID_PRIV_HDMI_DIV]		= &g12a_hdmi_div.hw,
>  		[CLKID_HDMI]			= &g12a_hdmi.hw,
>  		[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
> -		[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
> +		[CLKID_PRIV_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>  		[CLKID_MALI_0]			= &g12a_mali_0.hw,
>  		[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
> -		[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
> +		[CLKID_PRIV_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>  		[CLKID_MALI_1]			= &g12a_mali_1.hw,
>  		[CLKID_MALI]			= &g12a_mali.hw,
> -		[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
> +		[CLKID_PRIV_MPLL_50M_DIV]	= &g12a_mpll_50m_div.hw,
>  		[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
> -		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
> -		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
> -		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
> -		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
> -		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
> -		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
> -		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
> -		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
> -		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
> +		[CLKID_PRIV_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
> +		[CLKID_PRIV_SYS_PLL_DIV16]	= &g12a_sys_pll_div16.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN0]	= &g12a_cpu_clk_postmux0.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN1]	= &g12a_cpu_clk_postmux1.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN]	= &g12a_cpu_clk_dyn.hw,
>  		[CLKID_CPU_CLK]			= &g12b_cpu_clk.hw,
> -		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
> -		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
> -		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
> -		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
> -		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
> -		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
> -		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
> -		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
> -		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
> -		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
> -		[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
> -		[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
> -		[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
> +		[CLKID_PRIV_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
> +		[CLKID_PRIV_CPU_CLK_DIV16]	= &g12a_cpu_clk_div16.hw,
> +		[CLKID_PRIV_CPU_CLK_APB_DIV]	= &g12a_cpu_clk_apb_div.hw,
> +		[CLKID_PRIV_CPU_CLK_APB]	= &g12a_cpu_clk_apb.hw,
> +		[CLKID_PRIV_CPU_CLK_ATB_DIV]	= &g12a_cpu_clk_atb_div.hw,
> +		[CLKID_PRIV_CPU_CLK_ATB]	= &g12a_cpu_clk_atb.hw,
> +		[CLKID_PRIV_CPU_CLK_AXI_DIV]	= &g12a_cpu_clk_axi_div.hw,
> +		[CLKID_PRIV_CPU_CLK_AXI]	= &g12a_cpu_clk_axi.hw,
> +		[CLKID_PRIV_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
> +		[CLKID_PRIV_CPU_CLK_TRACE]	= &g12a_cpu_clk_trace.hw,
> +		[CLKID_PRIV_PCIE_PLL_DCO]	= &g12a_pcie_pll_dco.hw,
> +		[CLKID_PRIV_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
> +		[CLKID_PRIV_PCIE_PLL_OD]	= &g12a_pcie_pll_od.hw,
>  		[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
> -		[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
> -		[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
> +		[CLKID_PRIV_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
> +		[CLKID_PRIV_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>  		[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
> -		[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
> -		[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
> +		[CLKID_PRIV_VDEC_HEVC_SEL]	= &g12a_vdec_hevc_sel.hw,
> +		[CLKID_PRIV_VDEC_HEVC_DIV]	= &g12a_vdec_hevc_div.hw,
>  		[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
> -		[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
> -		[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
> +		[CLKID_PRIV_VDEC_HEVCF_SEL]	= &g12a_vdec_hevcf_sel.hw,
> +		[CLKID_PRIV_VDEC_HEVCF_DIV]	= &g12a_vdec_hevcf_div.hw,
>  		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
> -		[CLKID_TS_DIV]			= &g12a_ts_div.hw,
> +		[CLKID_PRIV_TS_DIV]		= &g12a_ts_div.hw,
>  		[CLKID_TS]			= &g12a_ts.hw,
> -		[CLKID_SYS1_PLL_DCO]		= &g12b_sys1_pll_dco.hw,
> -		[CLKID_SYS1_PLL]		= &g12b_sys1_pll.hw,
> -		[CLKID_SYS1_PLL_DIV16_EN]	= &g12b_sys1_pll_div16_en.hw,
> -		[CLKID_SYS1_PLL_DIV16]		= &g12b_sys1_pll_div16.hw,
> -		[CLKID_CPUB_CLK_DYN0_SEL]	= &g12b_cpub_clk_premux0.hw,
> -		[CLKID_CPUB_CLK_DYN0_DIV]	= &g12b_cpub_clk_mux0_div.hw,
> -		[CLKID_CPUB_CLK_DYN0]		= &g12b_cpub_clk_postmux0.hw,
> -		[CLKID_CPUB_CLK_DYN1_SEL]	= &g12b_cpub_clk_premux1.hw,
> -		[CLKID_CPUB_CLK_DYN1_DIV]	= &g12b_cpub_clk_mux1_div.hw,
> -		[CLKID_CPUB_CLK_DYN1]		= &g12b_cpub_clk_postmux1.hw,
> -		[CLKID_CPUB_CLK_DYN]		= &g12b_cpub_clk_dyn.hw,
> +		[CLKID_PRIV_SYS1_PLL_DCO]	= &g12b_sys1_pll_dco.hw,
> +		[CLKID_PRIV_SYS1_PLL]		= &g12b_sys1_pll.hw,
> +		[CLKID_PRIV_SYS1_PLL_DIV16_EN]	= &g12b_sys1_pll_div16_en.hw,
> +		[CLKID_PRIV_SYS1_PLL_DIV16]	= &g12b_sys1_pll_div16.hw,
> +		[CLKID_PRIV_CPUB_CLK_DYN0_SEL]	= &g12b_cpub_clk_premux0.hw,
> +		[CLKID_PRIV_CPUB_CLK_DYN0_DIV]	= &g12b_cpub_clk_mux0_div.hw,
> +		[CLKID_PRIV_CPUB_CLK_DYN0]	= &g12b_cpub_clk_postmux0.hw,
> +		[CLKID_PRIV_CPUB_CLK_DYN1_SEL]	= &g12b_cpub_clk_premux1.hw,
> +		[CLKID_PRIV_CPUB_CLK_DYN1_DIV]	= &g12b_cpub_clk_mux1_div.hw,
> +		[CLKID_PRIV_CPUB_CLK_DYN1]	= &g12b_cpub_clk_postmux1.hw,
> +		[CLKID_PRIV_CPUB_CLK_DYN]	= &g12b_cpub_clk_dyn.hw,
>  		[CLKID_CPUB_CLK]		= &g12b_cpub_clk.hw,
> -		[CLKID_CPUB_CLK_DIV16_EN]	= &g12b_cpub_clk_div16_en.hw,
> -		[CLKID_CPUB_CLK_DIV16]		= &g12b_cpub_clk_div16.hw,
> -		[CLKID_CPUB_CLK_DIV2]		= &g12b_cpub_clk_div2.hw,
> -		[CLKID_CPUB_CLK_DIV3]		= &g12b_cpub_clk_div3.hw,
> -		[CLKID_CPUB_CLK_DIV4]		= &g12b_cpub_clk_div4.hw,
> -		[CLKID_CPUB_CLK_DIV5]		= &g12b_cpub_clk_div5.hw,
> -		[CLKID_CPUB_CLK_DIV6]		= &g12b_cpub_clk_div6.hw,
> -		[CLKID_CPUB_CLK_DIV7]		= &g12b_cpub_clk_div7.hw,
> -		[CLKID_CPUB_CLK_DIV8]		= &g12b_cpub_clk_div8.hw,
> -		[CLKID_CPUB_CLK_APB_SEL]	= &g12b_cpub_clk_apb_sel.hw,
> -		[CLKID_CPUB_CLK_APB]		= &g12b_cpub_clk_apb.hw,
> -		[CLKID_CPUB_CLK_ATB_SEL]	= &g12b_cpub_clk_atb_sel.hw,
> -		[CLKID_CPUB_CLK_ATB]		= &g12b_cpub_clk_atb.hw,
> -		[CLKID_CPUB_CLK_AXI_SEL]	= &g12b_cpub_clk_axi_sel.hw,
> -		[CLKID_CPUB_CLK_AXI]		= &g12b_cpub_clk_axi.hw,
> -		[CLKID_CPUB_CLK_TRACE_SEL]	= &g12b_cpub_clk_trace_sel.hw,
> -		[CLKID_CPUB_CLK_TRACE]		= &g12b_cpub_clk_trace.hw,
> -		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
> -		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
> +		[CLKID_PRIV_CPUB_CLK_DIV16_EN]	= &g12b_cpub_clk_div16_en.hw,
> +		[CLKID_PRIV_CPUB_CLK_DIV16]	= &g12b_cpub_clk_div16.hw,
> +		[CLKID_PRIV_CPUB_CLK_DIV2]	= &g12b_cpub_clk_div2.hw,
> +		[CLKID_PRIV_CPUB_CLK_DIV3]	= &g12b_cpub_clk_div3.hw,
> +		[CLKID_PRIV_CPUB_CLK_DIV4]	= &g12b_cpub_clk_div4.hw,
> +		[CLKID_PRIV_CPUB_CLK_DIV5]	= &g12b_cpub_clk_div5.hw,
> +		[CLKID_PRIV_CPUB_CLK_DIV6]	= &g12b_cpub_clk_div6.hw,
> +		[CLKID_PRIV_CPUB_CLK_DIV7]	= &g12b_cpub_clk_div7.hw,
> +		[CLKID_PRIV_CPUB_CLK_DIV8]	= &g12b_cpub_clk_div8.hw,
> +		[CLKID_PRIV_CPUB_CLK_APB_SEL]	= &g12b_cpub_clk_apb_sel.hw,
> +		[CLKID_PRIV_CPUB_CLK_APB]	= &g12b_cpub_clk_apb.hw,
> +		[CLKID_PRIV_CPUB_CLK_ATB_SEL]	= &g12b_cpub_clk_atb_sel.hw,
> +		[CLKID_PRIV_CPUB_CLK_ATB]	= &g12b_cpub_clk_atb.hw,
> +		[CLKID_PRIV_CPUB_CLK_AXI_SEL]	= &g12b_cpub_clk_axi_sel.hw,
> +		[CLKID_PRIV_CPUB_CLK_AXI]	= &g12b_cpub_clk_axi.hw,
> +		[CLKID_PRIV_CPUB_CLK_TRACE_SEL]	= &g12b_cpub_clk_trace_sel.hw,
> +		[CLKID_PRIV_CPUB_CLK_TRACE]	= &g12b_cpub_clk_trace.hw,
> +		[CLKID_PRIV_SPICC0_SCLK_SEL]	= &g12a_spicc0_sclk_sel.hw,
> +		[CLKID_PRIV_SPICC0_SCLK_DIV]	= &g12a_spicc0_sclk_div.hw,
>  		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
> -		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
> -		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
> +		[CLKID_PRIV_SPICC1_SCLK_SEL]	= &g12a_spicc1_sclk_sel.hw,
> +		[CLKID_PRIV_SPICC1_SCLK_DIV]	= &g12a_spicc1_sclk_div.hw,
>  		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
> -		[CLKID_NNA_AXI_CLK_SEL]		= &sm1_nna_axi_clk_sel.hw,
> -		[CLKID_NNA_AXI_CLK_DIV]		= &sm1_nna_axi_clk_div.hw,
> +		[CLKID_PRIV_NNA_AXI_CLK_SEL]	= &sm1_nna_axi_clk_sel.hw,
> +		[CLKID_PRIV_NNA_AXI_CLK_DIV]	= &sm1_nna_axi_clk_div.hw,
>  		[CLKID_NNA_AXI_CLK]		= &sm1_nna_axi_clk.hw,
> -		[CLKID_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
> -		[CLKID_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
> +		[CLKID_PRIV_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
> +		[CLKID_PRIV_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
>  		[CLKID_NNA_CORE_CLK]		= &sm1_nna_core_clk.hw,
>  		[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
> -		[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
> +		[CLKID_PRIV_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>  		[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
>  		[NR_CLKS]			= NULL,
>  	},
> @@ -4748,8 +4748,8 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
>  		[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
>  		[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
>  		[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
> -		[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
> -		[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
> +		[CLKID_PRIV_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
> +		[CLKID_PRIV_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>  		[CLKID_CLK81]			= &g12a_clk81.hw,
>  		[CLKID_MPLL0]			= &g12a_mpll0.hw,
>  		[CLKID_MPLL1]			= &g12a_mpll1.hw,
> @@ -4800,25 +4800,25 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
>  		[CLKID_UART2]			= &g12a_uart2.hw,
>  		[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
>  		[CLKID_GIC]			= &g12a_gic.hw,
> -		[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
> -		[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
> +		[CLKID_PRIV_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
> +		[CLKID_PRIV_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>  		[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
> -		[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
> -		[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
> +		[CLKID_PRIV_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
> +		[CLKID_PRIV_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>  		[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
> -		[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
> -		[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
> +		[CLKID_PRIV_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
> +		[CLKID_PRIV_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>  		[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
> -		[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
> -		[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
> -		[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
> -		[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
> -		[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
> -		[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
> -		[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
> -		[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
> -		[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
> -		[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
> +		[CLKID_PRIV_MPLL0_DIV]		= &g12a_mpll0_div.hw,
> +		[CLKID_PRIV_MPLL1_DIV]		= &g12a_mpll1_div.hw,
> +		[CLKID_PRIV_MPLL2_DIV]		= &g12a_mpll2_div.hw,
> +		[CLKID_PRIV_MPLL3_DIV]		= &g12a_mpll3_div.hw,
> +		[CLKID_PRIV_FCLK_DIV2_DIV]	= &g12a_fclk_div2_div.hw,
> +		[CLKID_PRIV_FCLK_DIV3_DIV]	= &g12a_fclk_div3_div.hw,
> +		[CLKID_PRIV_FCLK_DIV4_DIV]	= &g12a_fclk_div4_div.hw,
> +		[CLKID_PRIV_FCLK_DIV5_DIV]	= &g12a_fclk_div5_div.hw,
> +		[CLKID_PRIV_FCLK_DIV7_DIV]	= &g12a_fclk_div7_div.hw,
> +		[CLKID_PRIV_FCLK_DIV2P5_DIV]	= &g12a_fclk_div2p5_div.hw,
>  		[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
>  		[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
>  		[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
> @@ -4839,56 +4839,56 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
>  		[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
>  		[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
>  		[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
> -		[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
> -		[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
> -		[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
> -		[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
> +		[CLKID_PRIV_FIXED_PLL_DCO]	= &g12a_fixed_pll_dco.hw,
> +		[CLKID_PRIV_SYS_PLL_DCO]	= &g12a_sys_pll_dco.hw,
> +		[CLKID_PRIV_GP0_PLL_DCO]	= &g12a_gp0_pll_dco.hw,
> +		[CLKID_PRIV_HIFI_PLL_DCO]	= &g12a_hifi_pll_dco.hw,
>  		[CLKID_DMA]			= &g12a_dma.hw,
>  		[CLKID_EFUSE]			= &g12a_efuse.hw,
>  		[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
>  		[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
>  		[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
> -		[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
> +		[CLKID_PRIV_MPLL_PREDIV]	= &g12a_mpll_prediv.hw,
>  		[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
> -		[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
> +		[CLKID_PRIV_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>  		[CLKID_VPU_0]			= &g12a_vpu_0.hw,
>  		[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
> -		[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
> +		[CLKID_PRIV_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>  		[CLKID_VPU_1]			= &g12a_vpu_1.hw,
>  		[CLKID_VPU]			= &g12a_vpu.hw,
>  		[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
> -		[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
> +		[CLKID_PRIV_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>  		[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
>  		[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
> -		[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
> +		[CLKID_PRIV_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>  		[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
>  		[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
>  		[CLKID_VAPB]			= &g12a_vapb.hw,
> -		[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
> -		[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
> -		[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
> +		[CLKID_PRIV_HDMI_PLL_DCO]	= &g12a_hdmi_pll_dco.hw,
> +		[CLKID_PRIV_HDMI_PLL_OD]	= &g12a_hdmi_pll_od.hw,
> +		[CLKID_PRIV_HDMI_PLL_OD2]	= &g12a_hdmi_pll_od2.hw,
>  		[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
>  		[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
> -		[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
> -		[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
> -		[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
> -		[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
> -		[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
> -		[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
> -		[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
> -		[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
> +		[CLKID_PRIV_VID_PLL_SEL]	= &g12a_vid_pll_sel.hw,
> +		[CLKID_PRIV_VID_PLL_DIV]	= &g12a_vid_pll.hw,
> +		[CLKID_PRIV_VCLK_SEL]		= &g12a_vclk_sel.hw,
> +		[CLKID_PRIV_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
> +		[CLKID_PRIV_VCLK_INPUT]		= &g12a_vclk_input.hw,
> +		[CLKID_PRIV_VCLK2_INPUT]	= &g12a_vclk2_input.hw,
> +		[CLKID_PRIV_VCLK_DIV]		= &g12a_vclk_div.hw,
> +		[CLKID_PRIV_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>  		[CLKID_VCLK]			= &g12a_vclk.hw,
>  		[CLKID_VCLK2]			= &g12a_vclk2.hw,
>  		[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
> -		[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
> -		[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
> -		[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
> -		[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
> +		[CLKID_PRIV_VCLK_DIV2_EN]	= &g12a_vclk_div2_en.hw,
> +		[CLKID_PRIV_VCLK_DIV4_EN]	= &g12a_vclk_div4_en.hw,
> +		[CLKID_PRIV_VCLK_DIV6_EN]	= &g12a_vclk_div6_en.hw,
> +		[CLKID_PRIV_VCLK_DIV12_EN]	= &g12a_vclk_div12_en.hw,
>  		[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
> -		[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
> -		[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
> -		[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
> -		[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
> +		[CLKID_PRIV_VCLK2_DIV2_EN]	= &g12a_vclk2_div2_en.hw,
> +		[CLKID_PRIV_VCLK2_DIV4_EN]	= &g12a_vclk2_div4_en.hw,
> +		[CLKID_PRIV_VCLK2_DIV6_EN]	= &g12a_vclk2_div6_en.hw,
> +		[CLKID_PRIV_VCLK2_DIV12_EN]	= &g12a_vclk2_div12_en.hw,
>  		[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
>  		[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
>  		[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
> @@ -4897,89 +4897,89 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
>  		[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
>  		[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
>  		[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
> -		[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
> -		[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
> -		[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
> -		[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
> +		[CLKID_PRIV_CTS_ENCI_SEL]	= &g12a_cts_enci_sel.hw,
> +		[CLKID_PRIV_CTS_ENCP_SEL]	= &g12a_cts_encp_sel.hw,
> +		[CLKID_PRIV_CTS_VDAC_SEL]	= &g12a_cts_vdac_sel.hw,
> +		[CLKID_PRIV_HDMI_TX_SEL]	= &g12a_hdmi_tx_sel.hw,
>  		[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
>  		[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
>  		[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
>  		[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
> -		[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
> -		[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
> +		[CLKID_PRIV_HDMI_SEL]		= &g12a_hdmi_sel.hw,
> +		[CLKID_PRIV_HDMI_DIV]		= &g12a_hdmi_div.hw,
>  		[CLKID_HDMI]			= &g12a_hdmi.hw,
>  		[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
> -		[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
> +		[CLKID_PRIV_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>  		[CLKID_MALI_0]			= &g12a_mali_0.hw,
>  		[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
> -		[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
> +		[CLKID_PRIV_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>  		[CLKID_MALI_1]			= &g12a_mali_1.hw,
>  		[CLKID_MALI]			= &g12a_mali.hw,
> -		[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
> +		[CLKID_PRIV_MPLL_50M_DIV]	= &g12a_mpll_50m_div.hw,
>  		[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
> -		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
> -		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
> -		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
> -		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
> -		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
> -		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
> -		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
> -		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
> -		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
> +		[CLKID_PRIV_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
> +		[CLKID_PRIV_SYS_PLL_DIV16]	= &g12a_sys_pll_div16.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN0]	= &g12a_cpu_clk_postmux0.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN1]	= &g12a_cpu_clk_postmux1.hw,
> +		[CLKID_PRIV_CPU_CLK_DYN]	= &g12a_cpu_clk_dyn.hw,
>  		[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,
> -		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
> -		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
> -		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
> -		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
> -		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
> -		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
> -		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
> -		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
> -		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
> -		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
> -		[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
> -		[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
> -		[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
> +		[CLKID_PRIV_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
> +		[CLKID_PRIV_CPU_CLK_DIV16]	= &g12a_cpu_clk_div16.hw,
> +		[CLKID_PRIV_CPU_CLK_APB_DIV]	= &g12a_cpu_clk_apb_div.hw,
> +		[CLKID_PRIV_CPU_CLK_APB]	= &g12a_cpu_clk_apb.hw,
> +		[CLKID_PRIV_CPU_CLK_ATB_DIV]	= &g12a_cpu_clk_atb_div.hw,
> +		[CLKID_PRIV_CPU_CLK_ATB]	= &g12a_cpu_clk_atb.hw,
> +		[CLKID_PRIV_CPU_CLK_AXI_DIV]	= &g12a_cpu_clk_axi_div.hw,
> +		[CLKID_PRIV_CPU_CLK_AXI]	= &g12a_cpu_clk_axi.hw,
> +		[CLKID_PRIV_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
> +		[CLKID_PRIV_CPU_CLK_TRACE]	= &g12a_cpu_clk_trace.hw,
> +		[CLKID_PRIV_PCIE_PLL_DCO]	= &g12a_pcie_pll_dco.hw,
> +		[CLKID_PRIV_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
> +		[CLKID_PRIV_PCIE_PLL_OD]	= &g12a_pcie_pll_od.hw,
>  		[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
> -		[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
> -		[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
> +		[CLKID_PRIV_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
> +		[CLKID_PRIV_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>  		[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
> -		[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
> -		[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
> +		[CLKID_PRIV_VDEC_HEVC_SEL]	= &g12a_vdec_hevc_sel.hw,
> +		[CLKID_PRIV_VDEC_HEVC_DIV]	= &g12a_vdec_hevc_div.hw,
>  		[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
> -		[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
> -		[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
> +		[CLKID_PRIV_VDEC_HEVCF_SEL]	= &g12a_vdec_hevcf_sel.hw,
> +		[CLKID_PRIV_VDEC_HEVCF_DIV]	= &g12a_vdec_hevcf_div.hw,
>  		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
> -		[CLKID_TS_DIV]			= &g12a_ts_div.hw,
> +		[CLKID_PRIV_TS_DIV]		= &g12a_ts_div.hw,
>  		[CLKID_TS]			= &g12a_ts.hw,
> -		[CLKID_GP1_PLL_DCO]		= &sm1_gp1_pll_dco.hw,
> +		[CLKID_PRIV_GP1_PLL_DCO]	= &sm1_gp1_pll_dco.hw,
>  		[CLKID_GP1_PLL]			= &sm1_gp1_pll.hw,
> -		[CLKID_DSU_CLK_DYN0_SEL]	= &sm1_dsu_clk_premux0.hw,
> -		[CLKID_DSU_CLK_DYN0_DIV]	= &sm1_dsu_clk_premux1.hw,
> -		[CLKID_DSU_CLK_DYN0]		= &sm1_dsu_clk_mux0_div.hw,
> -		[CLKID_DSU_CLK_DYN1_SEL]	= &sm1_dsu_clk_postmux0.hw,
> -		[CLKID_DSU_CLK_DYN1_DIV]	= &sm1_dsu_clk_mux1_div.hw,
> -		[CLKID_DSU_CLK_DYN1]		= &sm1_dsu_clk_postmux1.hw,
> -		[CLKID_DSU_CLK_DYN]		= &sm1_dsu_clk_dyn.hw,
> -		[CLKID_DSU_CLK_FINAL]		= &sm1_dsu_final_clk.hw,
> +		[CLKID_PRIV_DSU_CLK_DYN0_SEL]	= &sm1_dsu_clk_premux0.hw,
> +		[CLKID_PRIV_DSU_CLK_DYN0_DIV]	= &sm1_dsu_clk_premux1.hw,
> +		[CLKID_PRIV_DSU_CLK_DYN0]	= &sm1_dsu_clk_mux0_div.hw,
> +		[CLKID_PRIV_DSU_CLK_DYN1_SEL]	= &sm1_dsu_clk_postmux0.hw,
> +		[CLKID_PRIV_DSU_CLK_DYN1_DIV]	= &sm1_dsu_clk_mux1_div.hw,
> +		[CLKID_PRIV_DSU_CLK_DYN1]	= &sm1_dsu_clk_postmux1.hw,
> +		[CLKID_PRIV_DSU_CLK_DYN]	= &sm1_dsu_clk_dyn.hw,
> +		[CLKID_PRIV_DSU_CLK_FINAL]	= &sm1_dsu_final_clk.hw,
>  		[CLKID_DSU_CLK]			= &sm1_dsu_clk.hw,
>  		[CLKID_CPU1_CLK]		= &sm1_cpu1_clk.hw,
>  		[CLKID_CPU2_CLK]		= &sm1_cpu2_clk.hw,
>  		[CLKID_CPU3_CLK]		= &sm1_cpu3_clk.hw,
> -		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
> -		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
> +		[CLKID_PRIV_SPICC0_SCLK_SEL]	= &g12a_spicc0_sclk_sel.hw,
> +		[CLKID_PRIV_SPICC0_SCLK_DIV]	= &g12a_spicc0_sclk_div.hw,
>  		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
> -		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
> -		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
> +		[CLKID_PRIV_SPICC1_SCLK_SEL]	= &g12a_spicc1_sclk_sel.hw,
> +		[CLKID_PRIV_SPICC1_SCLK_DIV]	= &g12a_spicc1_sclk_div.hw,
>  		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
> -		[CLKID_NNA_AXI_CLK_SEL]		= &sm1_nna_axi_clk_sel.hw,
> -		[CLKID_NNA_AXI_CLK_DIV]		= &sm1_nna_axi_clk_div.hw,
> +		[CLKID_PRIV_NNA_AXI_CLK_SEL]	= &sm1_nna_axi_clk_sel.hw,
> +		[CLKID_PRIV_NNA_AXI_CLK_DIV]	= &sm1_nna_axi_clk_div.hw,
>  		[CLKID_NNA_AXI_CLK]		= &sm1_nna_axi_clk.hw,
> -		[CLKID_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
> -		[CLKID_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
> +		[CLKID_PRIV_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
> +		[CLKID_PRIV_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
>  		[CLKID_NNA_CORE_CLK]		= &sm1_nna_core_clk.hw,
>  		[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
> -		[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
> +		[CLKID_PRIV_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>  		[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
>  		[NR_CLKS]			= NULL,
>  	},
> @@ -5246,7 +5246,7 @@ static int meson_g12a_dvfs_setup_common(struct device *dev,
>  	struct clk_hw *xtal;
>  	int ret;
>  
> -	xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
> +	xtal = clk_hw_get_parent_by_index(hws[CLKID_PRIV_CPU_CLK_DYN1_SEL], 0);
>  
>  	/* Setup clock notifier for cpu_clk_postmux0 */
>  	g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
> @@ -5284,7 +5284,7 @@ static int meson_g12b_dvfs_setup(struct platform_device *pdev)
>  	if (ret)
>  		return ret;
>  
> -	xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
> +	xtal = clk_hw_get_parent_by_index(hws[CLKID_PRIV_CPU_CLK_DYN1_SEL], 0);
>  
>  	/* Setup clock notifier for cpu_clk mux */
>  	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw,
> diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
> index a97613df38b3..a57f4a9717db 100644
> --- a/drivers/clk/meson/g12a.h
> +++ b/drivers/clk/meson/g12a.h
> @@ -135,136 +135,136 @@
>   * to expose, such as the internal muxes and dividers of composite clocks,
>   * will remain defined here.
>   */
> -#define CLKID_MPEG_SEL				8
> -#define CLKID_MPEG_DIV				9
> -#define CLKID_SD_EMMC_A_CLK0_SEL		63
> -#define CLKID_SD_EMMC_A_CLK0_DIV		64
> -#define CLKID_SD_EMMC_B_CLK0_SEL		65
> -#define CLKID_SD_EMMC_B_CLK0_DIV		66
> -#define CLKID_SD_EMMC_C_CLK0_SEL		67
> -#define CLKID_SD_EMMC_C_CLK0_DIV		68
> -#define CLKID_MPLL0_DIV				69
> -#define CLKID_MPLL1_DIV				70
> -#define CLKID_MPLL2_DIV				71
> -#define CLKID_MPLL3_DIV				72
> -#define CLKID_MPLL_PREDIV			73
> -#define CLKID_FCLK_DIV2_DIV			75
> -#define CLKID_FCLK_DIV3_DIV			76
> -#define CLKID_FCLK_DIV4_DIV			77
> -#define CLKID_FCLK_DIV5_DIV			78
> -#define CLKID_FCLK_DIV7_DIV			79
> -#define CLKID_FCLK_DIV2P5_DIV			100
> -#define CLKID_FIXED_PLL_DCO			101
> -#define CLKID_SYS_PLL_DCO			102
> -#define CLKID_GP0_PLL_DCO			103
> -#define CLKID_HIFI_PLL_DCO			104
> -#define CLKID_VPU_0_DIV				111
> -#define CLKID_VPU_1_DIV				114
> -#define CLKID_VAPB_0_DIV			118
> -#define CLKID_VAPB_1_DIV			121
> -#define CLKID_HDMI_PLL_DCO			125
> -#define CLKID_HDMI_PLL_OD			126
> -#define CLKID_HDMI_PLL_OD2			127
> -#define CLKID_VID_PLL_SEL			130
> -#define CLKID_VID_PLL_DIV			131
> -#define CLKID_VCLK_SEL				132
> -#define CLKID_VCLK2_SEL				133
> -#define CLKID_VCLK_INPUT			134
> -#define CLKID_VCLK2_INPUT			135
> -#define CLKID_VCLK_DIV				136
> -#define CLKID_VCLK2_DIV				137
> -#define CLKID_VCLK_DIV2_EN			140
> -#define CLKID_VCLK_DIV4_EN			141
> -#define CLKID_VCLK_DIV6_EN			142
> -#define CLKID_VCLK_DIV12_EN			143
> -#define CLKID_VCLK2_DIV2_EN			144
> -#define CLKID_VCLK2_DIV4_EN			145
> -#define CLKID_VCLK2_DIV6_EN			146
> -#define CLKID_VCLK2_DIV12_EN			147
> -#define CLKID_CTS_ENCI_SEL			158
> -#define CLKID_CTS_ENCP_SEL			159
> -#define CLKID_CTS_VDAC_SEL			160
> -#define CLKID_HDMI_TX_SEL			161
> -#define CLKID_HDMI_SEL				166
> -#define CLKID_HDMI_DIV				167
> -#define CLKID_MALI_0_DIV			170
> -#define CLKID_MALI_1_DIV			173
> -#define CLKID_MPLL_50M_DIV			176
> -#define CLKID_SYS_PLL_DIV16_EN			178
> -#define CLKID_SYS_PLL_DIV16			179
> -#define CLKID_CPU_CLK_DYN0_SEL			180
> -#define CLKID_CPU_CLK_DYN0_DIV			181
> -#define CLKID_CPU_CLK_DYN0			182
> -#define CLKID_CPU_CLK_DYN1_SEL			183
> -#define CLKID_CPU_CLK_DYN1_DIV			184
> -#define CLKID_CPU_CLK_DYN1			185
> -#define CLKID_CPU_CLK_DYN			186
> -#define CLKID_CPU_CLK_DIV16_EN			188
> -#define CLKID_CPU_CLK_DIV16			189
> -#define CLKID_CPU_CLK_APB_DIV			190
> -#define CLKID_CPU_CLK_APB			191
> -#define CLKID_CPU_CLK_ATB_DIV			192
> -#define CLKID_CPU_CLK_ATB			193
> -#define CLKID_CPU_CLK_AXI_DIV			194
> -#define CLKID_CPU_CLK_AXI			195
> -#define CLKID_CPU_CLK_TRACE_DIV			196
> -#define CLKID_CPU_CLK_TRACE			197
> -#define CLKID_PCIE_PLL_DCO			198
> -#define CLKID_PCIE_PLL_DCO_DIV2			199
> -#define CLKID_PCIE_PLL_OD			200
> -#define CLKID_VDEC_1_SEL			202
> -#define CLKID_VDEC_1_DIV			203
> -#define CLKID_VDEC_HEVC_SEL			205
> -#define CLKID_VDEC_HEVC_DIV			206
> -#define CLKID_VDEC_HEVCF_SEL			208
> -#define CLKID_VDEC_HEVCF_DIV			209
> -#define CLKID_TS_DIV				211
> -#define CLKID_SYS1_PLL_DCO			213
> -#define CLKID_SYS1_PLL				214
> -#define CLKID_SYS1_PLL_DIV16_EN			215
> -#define CLKID_SYS1_PLL_DIV16			216
> -#define CLKID_CPUB_CLK_DYN0_SEL			217
> -#define CLKID_CPUB_CLK_DYN0_DIV			218
> -#define CLKID_CPUB_CLK_DYN0			219
> -#define CLKID_CPUB_CLK_DYN1_SEL			220
> -#define CLKID_CPUB_CLK_DYN1_DIV			221
> -#define CLKID_CPUB_CLK_DYN1			222
> -#define CLKID_CPUB_CLK_DYN			223
> -#define CLKID_CPUB_CLK_DIV16_EN			225
> -#define CLKID_CPUB_CLK_DIV16			226
> -#define CLKID_CPUB_CLK_DIV2			227
> -#define CLKID_CPUB_CLK_DIV3			228
> -#define CLKID_CPUB_CLK_DIV4			229
> -#define CLKID_CPUB_CLK_DIV5			230
> -#define CLKID_CPUB_CLK_DIV6			231
> -#define CLKID_CPUB_CLK_DIV7			232
> -#define CLKID_CPUB_CLK_DIV8			233
> -#define CLKID_CPUB_CLK_APB_SEL			234
> -#define CLKID_CPUB_CLK_APB			235
> -#define CLKID_CPUB_CLK_ATB_SEL			236
> -#define CLKID_CPUB_CLK_ATB			237
> -#define CLKID_CPUB_CLK_AXI_SEL			238
> -#define CLKID_CPUB_CLK_AXI			239
> -#define CLKID_CPUB_CLK_TRACE_SEL		240
> -#define CLKID_CPUB_CLK_TRACE			241
> -#define CLKID_GP1_PLL_DCO			242
> -#define CLKID_DSU_CLK_DYN0_SEL			244
> -#define CLKID_DSU_CLK_DYN0_DIV			245
> -#define CLKID_DSU_CLK_DYN0			246
> -#define CLKID_DSU_CLK_DYN1_SEL			247
> -#define CLKID_DSU_CLK_DYN1_DIV			248
> -#define CLKID_DSU_CLK_DYN1			249
> -#define CLKID_DSU_CLK_DYN			250
> -#define CLKID_DSU_CLK_FINAL			251
> -#define CLKID_SPICC0_SCLK_SEL			256
> -#define CLKID_SPICC0_SCLK_DIV			257
> -#define CLKID_SPICC1_SCLK_SEL			259
> -#define CLKID_SPICC1_SCLK_DIV			260
> -#define CLKID_NNA_AXI_CLK_SEL			262
> -#define CLKID_NNA_AXI_CLK_DIV			263
> -#define CLKID_NNA_CORE_CLK_SEL			265
> -#define CLKID_NNA_CORE_CLK_DIV			266
> -#define CLKID_MIPI_DSI_PXCLK_DIV		268
> +#define CLKID_PRIV_MPEG_SEL			8
> +#define CLKID_PRIV_MPEG_DIV			9
> +#define CLKID_PRIV_SD_EMMC_A_CLK0_SEL		63
> +#define CLKID_PRIV_SD_EMMC_A_CLK0_DIV		64
> +#define CLKID_PRIV_SD_EMMC_B_CLK0_SEL		65
> +#define CLKID_PRIV_SD_EMMC_B_CLK0_DIV		66
> +#define CLKID_PRIV_SD_EMMC_C_CLK0_SEL		67
> +#define CLKID_PRIV_SD_EMMC_C_CLK0_DIV		68
> +#define CLKID_PRIV_MPLL0_DIV			69
> +#define CLKID_PRIV_MPLL1_DIV			70
> +#define CLKID_PRIV_MPLL2_DIV			71
> +#define CLKID_PRIV_MPLL3_DIV			72
> +#define CLKID_PRIV_MPLL_PREDIV			73
> +#define CLKID_PRIV_FCLK_DIV2_DIV		75
> +#define CLKID_PRIV_FCLK_DIV3_DIV		76
> +#define CLKID_PRIV_FCLK_DIV4_DIV		77
> +#define CLKID_PRIV_FCLK_DIV5_DIV		78
> +#define CLKID_PRIV_FCLK_DIV7_DIV		79
> +#define CLKID_PRIV_FCLK_DIV2P5_DIV		100
> +#define CLKID_PRIV_FIXED_PLL_DCO		101
> +#define CLKID_PRIV_SYS_PLL_DCO			102
> +#define CLKID_PRIV_GP0_PLL_DCO			103
> +#define CLKID_PRIV_HIFI_PLL_DCO			104
> +#define CLKID_PRIV_VPU_0_DIV			111
> +#define CLKID_PRIV_VPU_1_DIV			114
> +#define CLKID_PRIV_VAPB_0_DIV			118
> +#define CLKID_PRIV_VAPB_1_DIV			121
> +#define CLKID_PRIV_HDMI_PLL_DCO			125
> +#define CLKID_PRIV_HDMI_PLL_OD			126
> +#define CLKID_PRIV_HDMI_PLL_OD2			127
> +#define CLKID_PRIV_VID_PLL_SEL			130
> +#define CLKID_PRIV_VID_PLL_DIV			131
> +#define CLKID_PRIV_VCLK_SEL			132
> +#define CLKID_PRIV_VCLK2_SEL			133
> +#define CLKID_PRIV_VCLK_INPUT			134
> +#define CLKID_PRIV_VCLK2_INPUT			135
> +#define CLKID_PRIV_VCLK_DIV			136
> +#define CLKID_PRIV_VCLK2_DIV			137
> +#define CLKID_PRIV_VCLK_DIV2_EN			140
> +#define CLKID_PRIV_VCLK_DIV4_EN			141
> +#define CLKID_PRIV_VCLK_DIV6_EN			142
> +#define CLKID_PRIV_VCLK_DIV12_EN		143
> +#define CLKID_PRIV_VCLK2_DIV2_EN		144
> +#define CLKID_PRIV_VCLK2_DIV4_EN		145
> +#define CLKID_PRIV_VCLK2_DIV6_EN		146
> +#define CLKID_PRIV_VCLK2_DIV12_EN		147
> +#define CLKID_PRIV_CTS_ENCI_SEL			158
> +#define CLKID_PRIV_CTS_ENCP_SEL			159
> +#define CLKID_PRIV_CTS_VDAC_SEL			160
> +#define CLKID_PRIV_HDMI_TX_SEL			161
> +#define CLKID_PRIV_HDMI_SEL			166
> +#define CLKID_PRIV_HDMI_DIV			167
> +#define CLKID_PRIV_MALI_0_DIV			170
> +#define CLKID_PRIV_MALI_1_DIV			173
> +#define CLKID_PRIV_MPLL_50M_DIV			176
> +#define CLKID_PRIV_SYS_PLL_DIV16_EN		178
> +#define CLKID_PRIV_SYS_PLL_DIV16		179
> +#define CLKID_PRIV_CPU_CLK_DYN0_SEL		180
> +#define CLKID_PRIV_CPU_CLK_DYN0_DIV		181
> +#define CLKID_PRIV_CPU_CLK_DYN0			182
> +#define CLKID_PRIV_CPU_CLK_DYN1_SEL		183
> +#define CLKID_PRIV_CPU_CLK_DYN1_DIV		184
> +#define CLKID_PRIV_CPU_CLK_DYN1			185
> +#define CLKID_PRIV_CPU_CLK_DYN			186
> +#define CLKID_PRIV_CPU_CLK_DIV16_EN		188
> +#define CLKID_PRIV_CPU_CLK_DIV16		189
> +#define CLKID_PRIV_CPU_CLK_APB_DIV		190
> +#define CLKID_PRIV_CPU_CLK_APB			191
> +#define CLKID_PRIV_CPU_CLK_ATB_DIV		192
> +#define CLKID_PRIV_CPU_CLK_ATB			193
> +#define CLKID_PRIV_CPU_CLK_AXI_DIV		194
> +#define CLKID_PRIV_CPU_CLK_AXI			195
> +#define CLKID_PRIV_CPU_CLK_TRACE_DIV		196
> +#define CLKID_PRIV_CPU_CLK_TRACE		197
> +#define CLKID_PRIV_PCIE_PLL_DCO			198
> +#define CLKID_PRIV_PCIE_PLL_DCO_DIV2		199
> +#define CLKID_PRIV_PCIE_PLL_OD			200
> +#define CLKID_PRIV_VDEC_1_SEL			202
> +#define CLKID_PRIV_VDEC_1_DIV			203
> +#define CLKID_PRIV_VDEC_HEVC_SEL		205
> +#define CLKID_PRIV_VDEC_HEVC_DIV		206
> +#define CLKID_PRIV_VDEC_HEVCF_SEL		208
> +#define CLKID_PRIV_VDEC_HEVCF_DIV		209
> +#define CLKID_PRIV_TS_DIV			211
> +#define CLKID_PRIV_SYS1_PLL_DCO			213
> +#define CLKID_PRIV_SYS1_PLL			214
> +#define CLKID_PRIV_SYS1_PLL_DIV16_EN		215
> +#define CLKID_PRIV_SYS1_PLL_DIV16		216
> +#define CLKID_PRIV_CPUB_CLK_DYN0_SEL		217
> +#define CLKID_PRIV_CPUB_CLK_DYN0_DIV		218
> +#define CLKID_PRIV_CPUB_CLK_DYN0		219
> +#define CLKID_PRIV_CPUB_CLK_DYN1_SEL		220
> +#define CLKID_PRIV_CPUB_CLK_DYN1_DIV		221
> +#define CLKID_PRIV_CPUB_CLK_DYN1		222
> +#define CLKID_PRIV_CPUB_CLK_DYN			223
> +#define CLKID_PRIV_CPUB_CLK_DIV16_EN		225
> +#define CLKID_PRIV_CPUB_CLK_DIV16		226
> +#define CLKID_PRIV_CPUB_CLK_DIV2		227
> +#define CLKID_PRIV_CPUB_CLK_DIV3		228
> +#define CLKID_PRIV_CPUB_CLK_DIV4		229
> +#define CLKID_PRIV_CPUB_CLK_DIV5		230
> +#define CLKID_PRIV_CPUB_CLK_DIV6		231
> +#define CLKID_PRIV_CPUB_CLK_DIV7		232
> +#define CLKID_PRIV_CPUB_CLK_DIV8		233
> +#define CLKID_PRIV_CPUB_CLK_APB_SEL		234
> +#define CLKID_PRIV_CPUB_CLK_APB			235
> +#define CLKID_PRIV_CPUB_CLK_ATB_SEL		236
> +#define CLKID_PRIV_CPUB_CLK_ATB			237
> +#define CLKID_PRIV_CPUB_CLK_AXI_SEL		238
> +#define CLKID_PRIV_CPUB_CLK_AXI			239
> +#define CLKID_PRIV_CPUB_CLK_TRACE_SEL		240
> +#define CLKID_PRIV_CPUB_CLK_TRACE		241
> +#define CLKID_PRIV_GP1_PLL_DCO			242
> +#define CLKID_PRIV_DSU_CLK_DYN0_SEL		244
> +#define CLKID_PRIV_DSU_CLK_DYN0_DIV		245
> +#define CLKID_PRIV_DSU_CLK_DYN0			246
> +#define CLKID_PRIV_DSU_CLK_DYN1_SEL		247
> +#define CLKID_PRIV_DSU_CLK_DYN1_DIV		248
> +#define CLKID_PRIV_DSU_CLK_DYN1			249
> +#define CLKID_PRIV_DSU_CLK_DYN			250
> +#define CLKID_PRIV_DSU_CLK_FINAL		251
> +#define CLKID_PRIV_SPICC0_SCLK_SEL		256
> +#define CLKID_PRIV_SPICC0_SCLK_DIV		257
> +#define CLKID_PRIV_SPICC1_SCLK_SEL		259
> +#define CLKID_PRIV_SPICC1_SCLK_DIV		260
> +#define CLKID_PRIV_NNA_AXI_CLK_SEL		262
> +#define CLKID_PRIV_NNA_AXI_CLK_DIV		263
> +#define CLKID_PRIV_NNA_CORE_CLK_SEL		265
> +#define CLKID_PRIV_NNA_CORE_CLK_DIV		266
> +#define CLKID_PRIV_MIPI_DSI_PXCLK_DIV		268
>  
>  #define NR_CLKS					271

Jerome Brunet May 30, 2023, 8:14 a.m. UTC | #2

On Tue 30 May 2023 at 09:38, Neil Armstrong <[e-mail]> wrote:

> In order to setup the DSI clock, let's make the unused VCLK2 clock path
> configuration via CCF.
>
> The nocache option is removed from following clocks:
> - vclk2_sel
> - vclk2_input
> - vclk2_div
> - vclk2
> - vclk_div1
> - vclk2_div2_en
> - vclk2_div4_en
> - vclk2_div6_en
> - vclk2_div12_en
> - vclk2_div2
> - vclk2_div4
> - vclk2_div6
> - vclk2_div12
> - cts_encl_sel
>
> The missing vclk2 reset sequence is handled via new clkc notifiers
> in order to reset the vclk2 after each rate change as done by Amlogic
> in the vendor implementation.
>
> In order to set a rate on cts_encl via the vclk2 clock path,
> the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order
> to keep CCF from selection a parent.
> The parents of cts_encl_sel & vclk2_sel are expected to be defined
> in DT.
>
> The following clock scheme is to be used for DSI:
>
> xtal
> \_ gp0_pll_dco
>    \_ gp0_pll
>       |- vclk2_sel
>       |  \_ vclk2_input
>       |     \_ vclk2_div
>       |        \_ vclk2
>       |           \_ vclk2_div1
>       |              \_ cts_encl_sel
>       |                 \_ cts_encl	-> to VPU LCD Encoder
>       |- mipi_dsi_pxclk_sel
>       \_ mipi_dsi_pxclk_div
>          \_ mipi_dsi_pxclk		-> to DSI controller
>
> The mipi_dsi_pxclk_div is set as RO in order to use the same GP0
> for mipi_dsi_pxclk and vclk2_input.

I don't think notifiers is the appropriate approach here.
Whenever there is clock change the motifiers would trigger an off/on of
the clock, regardless of the clock usage or state.
If you have several consummers on this vclk2, this would
cause glitches and maybe this is not desirable.

I think it would be better to handle the enable and reset with a
specific gate driver, in prepare() or enable(), and the give the clock
CLK_SET_RATE_GATE flag.

This would require the clock to be properly turn off before changing the
rate.

>
> Signed-off-by: Neil Armstrong <[e-mail]>
> ---
>  drivers/clk/meson/g12a.c | 131 +++++++++++++++++++++++++++++++++++++++++++----
>  1 file changed, 120 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
> index 461ebd79497c..e4053f4957d5 100644
> --- a/drivers/clk/meson/g12a.c
> +++ b/drivers/clk/meson/g12a.c
> @@ -3163,7 +3163,7 @@ static struct clk_regmap g12a_vclk2_sel = {
>  		.ops = &clk_regmap_mux_ops,
>  		.parent_hws = g12a_vclk_parent_hws,
>  		.num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
> -		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
> +		.flags = CLK_SET_RATE_NO_REPARENT,
>  	},
>  };
>  
> @@ -3191,7 +3191,6 @@ static struct clk_regmap g12a_vclk2_input = {
>  		.ops = &clk_regmap_gate_ops,
>  		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
>  		.num_parents = 1,
> -		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>  	},
>  };
>  
> @@ -3212,6 +3211,40 @@ static struct clk_regmap g12a_vclk_div = {
>  	},
>  };
>  
> +struct g12a_vclk_div_notifier {
> +	struct clk_regmap *clk;
> +	unsigned int offset;
> +	u8 en_bit_idx;
> +	u8 reset_bit_idx;
> +	struct notifier_block nb;
> +};
> +
> +static int g12a_vclk_div_notifier_cb(struct notifier_block *nb,
> +				  unsigned long event, void *data)
> +{
> +	struct g12a_vclk_div_notifier *nb_data =
> +		container_of(nb, struct g12a_vclk_div_notifier, nb);
> +
> +	switch (event) {
> +	case PRE_RATE_CHANGE:
> +		/* disable and reset vclk2 divider */
> +		regmap_update_bits(nb_data->clk->map, nb_data->offset,
> +				   BIT(nb_data->en_bit_idx) |
> +				   BIT(nb_data->reset_bit_idx),
> +				   BIT(nb_data->reset_bit_idx));
> +		return NOTIFY_OK;
> +	case POST_RATE_CHANGE:
> +		/* enabled and release reset */
> +		regmap_update_bits(nb_data->clk->map, nb_data->offset,
> +				   BIT(nb_data->en_bit_idx) |
> +				   BIT(nb_data->reset_bit_idx),
> +				   BIT(nb_data->en_bit_idx));
> +		return NOTIFY_OK;
> +	default:
> +		return NOTIFY_DONE;
> +	};
> +};
> +
>  static struct clk_regmap g12a_vclk2_div = {
>  	.data = &(struct clk_regmap_div_data){
>  		.offset = HHI_VIID_CLK_DIV,
> @@ -3225,10 +3258,18 @@ static struct clk_regmap g12a_vclk2_div = {
>  			&g12a_vclk2_input.hw
>  		},
>  		.num_parents = 1,
> -		.flags = CLK_GET_RATE_NOCACHE,
> +		.flags = CLK_DIVIDER_ROUND_CLOSEST,
>  	},
>  };
>  
> +static struct g12a_vclk_div_notifier g12a_vclk2_div_data = {
> +	.clk = &g12a_vclk2_div,
> +	.offset = HHI_VIID_CLK_DIV,
> +	.en_bit_idx = 16,
> +	.reset_bit_idx = 17,
> +	.nb.notifier_call = g12a_vclk_div_notifier_cb,
> +};
> +
>  static struct clk_regmap g12a_vclk = {
>  	.data = &(struct clk_regmap_gate_data){
>  		.offset = HHI_VID_CLK_CNTL,
> @@ -3243,6 +3284,33 @@ static struct clk_regmap g12a_vclk = {
>  	},
>  };
>  
> +struct g12a_vclk_reset_notifier {
> +	struct clk_regmap *clk;
> +	unsigned int offset;
> +	u8 bit_idx;
> +	struct notifier_block nb;
> +};
> +
> +static int g12a_vclk_notifier_cb(struct notifier_block *nb,
> +				  unsigned long event, void *data)
> +{
> +	struct g12a_vclk_reset_notifier *nb_data =
> +		container_of(nb, struct g12a_vclk_reset_notifier, nb);
> +
> +	switch (event) {
> +	case POST_RATE_CHANGE:
> +		/* reset vclk2 */
> +		regmap_update_bits(nb_data->clk->map, nb_data->offset,
> +				   BIT(nb_data->bit_idx), BIT(nb_data->bit_idx));
> +		regmap_update_bits(nb_data->clk->map, nb_data->offset,
> +				   BIT(nb_data->bit_idx), 0);
> +
> +		return NOTIFY_OK;
> +	default:
> +		return NOTIFY_DONE;
> +	};
> +}
> +
>  static struct clk_regmap g12a_vclk2 = {
>  	.data = &(struct clk_regmap_gate_data){
>  		.offset = HHI_VIID_CLK_CNTL,
> @@ -3253,10 +3321,17 @@ static struct clk_regmap g12a_vclk2 = {
>  		.ops = &clk_regmap_gate_ops,
>  		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
>  		.num_parents = 1,
> -		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +		.flags = CLK_SET_RATE_PARENT,
>  	},
>  };
>  
> +static struct g12a_vclk_reset_notifier g12a_vclk2_data = {
> +	.clk = &g12a_vclk2,
> +	.offset = HHI_VIID_CLK_CNTL,
> +	.bit_idx = 15,
> +	.nb.notifier_call = g12a_vclk_notifier_cb,
> +};
> +
>  static struct clk_regmap g12a_vclk_div1 = {
>  	.data = &(struct clk_regmap_gate_data){
>  		.offset = HHI_VID_CLK_CNTL,
> @@ -3337,7 +3412,7 @@ static struct clk_regmap g12a_vclk2_div1 = {
>  		.ops = &clk_regmap_gate_ops,
>  		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>  		.num_parents = 1,
> -		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +		.flags = CLK_SET_RATE_PARENT,
>  	},
>  };
>  
> @@ -3351,7 +3426,7 @@ static struct clk_regmap g12a_vclk2_div2_en = {
>  		.ops = &clk_regmap_gate_ops,
>  		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>  		.num_parents = 1,
> -		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +		.flags = CLK_SET_RATE_PARENT,
>  	},
>  };
>  
> @@ -3365,7 +3440,7 @@ static struct clk_regmap g12a_vclk2_div4_en = {
>  		.ops = &clk_regmap_gate_ops,
>  		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>  		.num_parents = 1,
> -		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +		.flags = CLK_SET_RATE_PARENT,
>  	},
>  };
>  
> @@ -3379,7 +3454,7 @@ static struct clk_regmap g12a_vclk2_div6_en = {
>  		.ops = &clk_regmap_gate_ops,
>  		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>  		.num_parents = 1,
> -		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +		.flags = CLK_SET_RATE_PARENT,
>  	},
>  };
>  
> @@ -3393,7 +3468,7 @@ static struct clk_regmap g12a_vclk2_div12_en = {
>  		.ops = &clk_regmap_gate_ops,
>  		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>  		.num_parents = 1,
> -		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +		.flags = CLK_SET_RATE_PARENT,
>  	},
>  };
>  
> @@ -3459,6 +3534,7 @@ static struct clk_fixed_factor g12a_vclk2_div2 = {
>  			&g12a_vclk2_div2_en.hw
>  		},
>  		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
>  	},
>  };
>  
> @@ -3472,6 +3548,7 @@ static struct clk_fixed_factor g12a_vclk2_div4 = {
>  			&g12a_vclk2_div4_en.hw
>  		},
>  		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
>  	},
>  };
>  
> @@ -3485,6 +3562,7 @@ static struct clk_fixed_factor g12a_vclk2_div6 = {
>  			&g12a_vclk2_div6_en.hw
>  		},
>  		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
>  	},
>  };
>  
> @@ -3498,6 +3576,7 @@ static struct clk_fixed_factor g12a_vclk2_div12 = {
>  			&g12a_vclk2_div12_en.hw
>  		},
>  		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
>  	},
>  };
>  
> @@ -3559,7 +3638,7 @@ static struct clk_regmap g12a_cts_encl_sel = {
>  		.ops = &clk_regmap_mux_ops,
>  		.parent_hws = g12a_cts_parent_hws,
>  		.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
> -		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
> +		.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
>  	},
>  };
>  
> @@ -3727,7 +3806,7 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
>  	},
>  	.hw.init = &(struct clk_init_data){
>  		.name = "mipi_dsi_pxclk_div",
> -		.ops = &clk_regmap_divider_ops,
> +		.ops = &clk_regmap_divider_ro_ops,
>  		.parent_hws = (const struct clk_hw *[]) {
>  			&g12a_mipi_dsi_pxclk_sel.hw
>  		},
> @@ -5421,6 +5500,32 @@ static int meson_g12a_dvfs_setup(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +static int meson_g12a_vclk_setup(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct clk *notifier_clk;
> +	int ret;
> +
> +	/* Setup clock notifier for vclk2 */
> +	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_vclk2.hw, DVFS_CON_ID);
> +	ret = devm_clk_notifier_register(dev, notifier_clk, &g12a_vclk2_data.nb);
> +	if (ret) {
> +		dev_err(dev, "failed to register the vlkc2 notifier\n");
> +		return ret;
> +	}
> +
> +	/* Setup clock notifier for vclk2_div */
> +	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_vclk2_div.hw, DVFS_CON_ID);
> +	ret = devm_clk_notifier_register(dev, notifier_clk,
> +					 &g12a_vclk2_div_data.nb);
> +	if (ret) {
> +		dev_err(dev, "failed to register the vclk2_div notifier\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
>  struct meson_g12a_data {
>  	const struct meson_eeclkc_data eeclkc_data;
>  	int (*dvfs_setup)(struct platform_device *pdev);
> @@ -5443,6 +5548,10 @@ static int meson_g12a_probe(struct platform_device *pdev)
>  	g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
>  				 eeclkc_data);
>  
> +	ret = meson_g12a_vclk_setup(pdev);
> +	if (ret)
> +		return ret;
> +
>  	if (g12a_data->dvfs_setup)
>  		return g12a_data->dvfs_setup(pdev);

Neil Armstrong May 30, 2023, 3:56 p.m. UTC | #3

On 30/05/2023 10:08, Jerome Brunet wrote:
> 
> On Tue 30 May 2023 at 09:38, Neil Armstrong <[e-mail]> wrote:
> 
>> Exposing should not be done in a single commit anymore due to
>> dt-bindings enforced rules.
>>
>> Prepend PRIV to the private CLK IDs so we can add new clock to
>> the bindings header and in a separate commit remove such private
>> define and switch to the public CLK IDs identifier.
>>
>> This refers to a discussion at [1] with Arnd and Krzysztof.
>>
>> [1] https://lore.kernel.org/all/[e-mail]/
>>
>> Signed-off-by: Neil Armstrong <[e-mail]>
> 
> I understand the discussion reported but I don't really like this CLKID_PRIV_
> It adds another layer of IDs.
> 
> I'd much prefer if we just expose all the IDs. That would comply with DT
> new policy and be much simpler in the long run.

While it would solve everything at long term, we'll still need to do the move
in 3 steps (add PRIV, add to bindings, remove PRIV defined), and we should still
decide how to handle NR_CLKS.

Neil

> 
>> ---
>>   drivers/clk/meson/g12a.c | 628 +++++++++++++++++++++++------------------------
>>   drivers/clk/meson/g12a.h | 260 ++++++++++----------
>>   2 files changed, 444 insertions(+), 444 deletions(-)
>>
>> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
>> index 310accf94830..d2e481ae2429 100644
>> --- a/drivers/clk/meson/g12a.c
>> +++ b/drivers/clk/meson/g12a.c
>> @@ -4255,8 +4255,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
>>   		[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
>>   		[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
>>   		[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
>> -		[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
>> -		[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>> +		[CLKID_PRIV_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
>> +		[CLKID_PRIV_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>>   		[CLKID_CLK81]			= &g12a_clk81.hw,
>>   		[CLKID_MPLL0]			= &g12a_mpll0.hw,
>>   		[CLKID_MPLL1]			= &g12a_mpll1.hw,
>> @@ -4307,25 +4307,25 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
>>   		[CLKID_UART2]			= &g12a_uart2.hw,
>>   		[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
>>   		[CLKID_GIC]			= &g12a_gic.hw,
>> -		[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
>> -		[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>> +		[CLKID_PRIV_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
>> +		[CLKID_PRIV_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>>   		[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
>> -		[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
>> -		[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>> +		[CLKID_PRIV_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
>> +		[CLKID_PRIV_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>>   		[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
>> -		[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
>> -		[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>> +		[CLKID_PRIV_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
>> +		[CLKID_PRIV_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>>   		[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
>> -		[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
>> -		[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
>> -		[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
>> -		[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
>> -		[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
>> -		[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
>> -		[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
>> -		[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
>> -		[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
>> -		[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
>> +		[CLKID_PRIV_MPLL0_DIV]		= &g12a_mpll0_div.hw,
>> +		[CLKID_PRIV_MPLL1_DIV]		= &g12a_mpll1_div.hw,
>> +		[CLKID_PRIV_MPLL2_DIV]		= &g12a_mpll2_div.hw,
>> +		[CLKID_PRIV_MPLL3_DIV]		= &g12a_mpll3_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV2_DIV]	= &g12a_fclk_div2_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV3_DIV]	= &g12a_fclk_div3_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV4_DIV]	= &g12a_fclk_div4_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV5_DIV]	= &g12a_fclk_div5_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV7_DIV]	= &g12a_fclk_div7_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV2P5_DIV]	= &g12a_fclk_div2p5_div.hw,
>>   		[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
>>   		[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
>>   		[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
>> @@ -4346,56 +4346,56 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
>>   		[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
>>   		[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
>>   		[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
>> -		[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
>> -		[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
>> -		[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
>> -		[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
>> +		[CLKID_PRIV_FIXED_PLL_DCO]	= &g12a_fixed_pll_dco.hw,
>> +		[CLKID_PRIV_SYS_PLL_DCO]	= &g12a_sys_pll_dco.hw,
>> +		[CLKID_PRIV_GP0_PLL_DCO]	= &g12a_gp0_pll_dco.hw,
>> +		[CLKID_PRIV_HIFI_PLL_DCO]	= &g12a_hifi_pll_dco.hw,
>>   		[CLKID_DMA]			= &g12a_dma.hw,
>>   		[CLKID_EFUSE]			= &g12a_efuse.hw,
>>   		[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
>>   		[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
>>   		[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
>> -		[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
>> +		[CLKID_PRIV_MPLL_PREDIV]	= &g12a_mpll_prediv.hw,
>>   		[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
>> -		[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>> +		[CLKID_PRIV_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>>   		[CLKID_VPU_0]			= &g12a_vpu_0.hw,
>>   		[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
>> -		[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>> +		[CLKID_PRIV_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>>   		[CLKID_VPU_1]			= &g12a_vpu_1.hw,
>>   		[CLKID_VPU]			= &g12a_vpu.hw,
>>   		[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
>> -		[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>> +		[CLKID_PRIV_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>>   		[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
>>   		[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
>> -		[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>> +		[CLKID_PRIV_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>>   		[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
>>   		[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
>>   		[CLKID_VAPB]			= &g12a_vapb.hw,
>> -		[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
>> -		[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
>> -		[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
>> +		[CLKID_PRIV_HDMI_PLL_DCO]	= &g12a_hdmi_pll_dco.hw,
>> +		[CLKID_PRIV_HDMI_PLL_OD]	= &g12a_hdmi_pll_od.hw,
>> +		[CLKID_PRIV_HDMI_PLL_OD2]	= &g12a_hdmi_pll_od2.hw,
>>   		[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
>>   		[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
>> -		[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
>> -		[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
>> -		[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
>> -		[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
>> -		[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
>> -		[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
>> -		[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
>> -		[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>> +		[CLKID_PRIV_VID_PLL_SEL]	= &g12a_vid_pll_sel.hw,
>> +		[CLKID_PRIV_VID_PLL_DIV]	= &g12a_vid_pll.hw,
>> +		[CLKID_PRIV_VCLK_SEL]		= &g12a_vclk_sel.hw,
>> +		[CLKID_PRIV_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
>> +		[CLKID_PRIV_VCLK_INPUT]		= &g12a_vclk_input.hw,
>> +		[CLKID_PRIV_VCLK2_INPUT]	= &g12a_vclk2_input.hw,
>> +		[CLKID_PRIV_VCLK_DIV]		= &g12a_vclk_div.hw,
>> +		[CLKID_PRIV_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>>   		[CLKID_VCLK]			= &g12a_vclk.hw,
>>   		[CLKID_VCLK2]			= &g12a_vclk2.hw,
>>   		[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
>> -		[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
>> -		[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
>> -		[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
>> -		[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
>> +		[CLKID_PRIV_VCLK_DIV2_EN]	= &g12a_vclk_div2_en.hw,
>> +		[CLKID_PRIV_VCLK_DIV4_EN]	= &g12a_vclk_div4_en.hw,
>> +		[CLKID_PRIV_VCLK_DIV6_EN]	= &g12a_vclk_div6_en.hw,
>> +		[CLKID_PRIV_VCLK_DIV12_EN]	= &g12a_vclk_div12_en.hw,
>>   		[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
>> -		[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
>> -		[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
>> -		[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
>> -		[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
>> +		[CLKID_PRIV_VCLK2_DIV2_EN]	= &g12a_vclk2_div2_en.hw,
>> +		[CLKID_PRIV_VCLK2_DIV4_EN]	= &g12a_vclk2_div4_en.hw,
>> +		[CLKID_PRIV_VCLK2_DIV6_EN]	= &g12a_vclk2_div6_en.hw,
>> +		[CLKID_PRIV_VCLK2_DIV12_EN]	= &g12a_vclk2_div12_en.hw,
>>   		[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
>>   		[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
>>   		[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
>> @@ -4404,69 +4404,69 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
>>   		[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
>>   		[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
>>   		[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
>> -		[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
>> -		[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
>> -		[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
>> -		[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
>> +		[CLKID_PRIV_CTS_ENCI_SEL]	= &g12a_cts_enci_sel.hw,
>> +		[CLKID_PRIV_CTS_ENCP_SEL]	= &g12a_cts_encp_sel.hw,
>> +		[CLKID_PRIV_CTS_VDAC_SEL]	= &g12a_cts_vdac_sel.hw,
>> +		[CLKID_PRIV_HDMI_TX_SEL]	= &g12a_hdmi_tx_sel.hw,
>>   		[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
>>   		[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
>>   		[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
>>   		[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
>> -		[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
>> -		[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
>> +		[CLKID_PRIV_HDMI_SEL]		= &g12a_hdmi_sel.hw,
>> +		[CLKID_PRIV_HDMI_DIV]		= &g12a_hdmi_div.hw,
>>   		[CLKID_HDMI]			= &g12a_hdmi.hw,
>>   		[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
>> -		[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>> +		[CLKID_PRIV_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>>   		[CLKID_MALI_0]			= &g12a_mali_0.hw,
>>   		[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
>> -		[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>> +		[CLKID_PRIV_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>>   		[CLKID_MALI_1]			= &g12a_mali_1.hw,
>>   		[CLKID_MALI]			= &g12a_mali.hw,
>> -		[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
>> +		[CLKID_PRIV_MPLL_50M_DIV]	= &g12a_mpll_50m_div.hw,
>>   		[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
>> -		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
>> -		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
>> -		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
>> -		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
>> -		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
>> -		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
>> -		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
>> -		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
>> -		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
>> +		[CLKID_PRIV_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
>> +		[CLKID_PRIV_SYS_PLL_DIV16]	= &g12a_sys_pll_div16.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN0]	= &g12a_cpu_clk_postmux0.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN1]	= &g12a_cpu_clk_postmux1.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN]	= &g12a_cpu_clk_dyn.hw,
>>   		[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,
>> -		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
>> -		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
>> -		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
>> -		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
>> -		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
>> -		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
>> -		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
>> -		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
>> -		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
>> -		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
>> -		[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
>> -		[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
>> -		[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
>> +		[CLKID_PRIV_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
>> +		[CLKID_PRIV_CPU_CLK_DIV16]	= &g12a_cpu_clk_div16.hw,
>> +		[CLKID_PRIV_CPU_CLK_APB_DIV]	= &g12a_cpu_clk_apb_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_APB]	= &g12a_cpu_clk_apb.hw,
>> +		[CLKID_PRIV_CPU_CLK_ATB_DIV]	= &g12a_cpu_clk_atb_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_ATB]	= &g12a_cpu_clk_atb.hw,
>> +		[CLKID_PRIV_CPU_CLK_AXI_DIV]	= &g12a_cpu_clk_axi_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_AXI]	= &g12a_cpu_clk_axi.hw,
>> +		[CLKID_PRIV_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_TRACE]	= &g12a_cpu_clk_trace.hw,
>> +		[CLKID_PRIV_PCIE_PLL_DCO]	= &g12a_pcie_pll_dco.hw,
>> +		[CLKID_PRIV_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
>> +		[CLKID_PRIV_PCIE_PLL_OD]	= &g12a_pcie_pll_od.hw,
>>   		[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
>> -		[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
>> -		[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>> +		[CLKID_PRIV_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
>> +		[CLKID_PRIV_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>>   		[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
>> -		[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
>> -		[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
>> +		[CLKID_PRIV_VDEC_HEVC_SEL]	= &g12a_vdec_hevc_sel.hw,
>> +		[CLKID_PRIV_VDEC_HEVC_DIV]	= &g12a_vdec_hevc_div.hw,
>>   		[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
>> -		[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
>> -		[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
>> +		[CLKID_PRIV_VDEC_HEVCF_SEL]	= &g12a_vdec_hevcf_sel.hw,
>> +		[CLKID_PRIV_VDEC_HEVCF_DIV]	= &g12a_vdec_hevcf_div.hw,
>>   		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
>> -		[CLKID_TS_DIV]			= &g12a_ts_div.hw,
>> +		[CLKID_PRIV_TS_DIV]		= &g12a_ts_div.hw,
>>   		[CLKID_TS]			= &g12a_ts.hw,
>> -		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
>> -		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
>> +		[CLKID_PRIV_SPICC0_SCLK_SEL]	= &g12a_spicc0_sclk_sel.hw,
>> +		[CLKID_PRIV_SPICC0_SCLK_DIV]	= &g12a_spicc0_sclk_div.hw,
>>   		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
>> -		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
>> -		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
>> +		[CLKID_PRIV_SPICC1_SCLK_SEL]	= &g12a_spicc1_sclk_sel.hw,
>> +		[CLKID_PRIV_SPICC1_SCLK_DIV]	= &g12a_spicc1_sclk_div.hw,
>>   		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
>>   		[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
>> -		[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>> +		[CLKID_PRIV_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>>   		[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
>>   		[NR_CLKS]			= NULL,
>>   	},
>> @@ -4484,8 +4484,8 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
>>   		[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
>>   		[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
>>   		[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
>> -		[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
>> -		[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>> +		[CLKID_PRIV_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
>> +		[CLKID_PRIV_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>>   		[CLKID_CLK81]			= &g12a_clk81.hw,
>>   		[CLKID_MPLL0]			= &g12a_mpll0.hw,
>>   		[CLKID_MPLL1]			= &g12a_mpll1.hw,
>> @@ -4536,25 +4536,25 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
>>   		[CLKID_UART2]			= &g12a_uart2.hw,
>>   		[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
>>   		[CLKID_GIC]			= &g12a_gic.hw,
>> -		[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
>> -		[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>> +		[CLKID_PRIV_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
>> +		[CLKID_PRIV_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>>   		[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
>> -		[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
>> -		[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>> +		[CLKID_PRIV_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
>> +		[CLKID_PRIV_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>>   		[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
>> -		[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
>> -		[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>> +		[CLKID_PRIV_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
>> +		[CLKID_PRIV_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>>   		[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
>> -		[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
>> -		[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
>> -		[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
>> -		[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
>> -		[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
>> -		[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
>> -		[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
>> -		[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
>> -		[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
>> -		[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
>> +		[CLKID_PRIV_MPLL0_DIV]		= &g12a_mpll0_div.hw,
>> +		[CLKID_PRIV_MPLL1_DIV]		= &g12a_mpll1_div.hw,
>> +		[CLKID_PRIV_MPLL2_DIV]		= &g12a_mpll2_div.hw,
>> +		[CLKID_PRIV_MPLL3_DIV]		= &g12a_mpll3_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV2_DIV]	= &g12a_fclk_div2_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV3_DIV]	= &g12a_fclk_div3_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV4_DIV]	= &g12a_fclk_div4_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV5_DIV]	= &g12a_fclk_div5_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV7_DIV]	= &g12a_fclk_div7_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV2P5_DIV]	= &g12a_fclk_div2p5_div.hw,
>>   		[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
>>   		[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
>>   		[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
>> @@ -4575,56 +4575,56 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
>>   		[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
>>   		[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
>>   		[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
>> -		[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
>> -		[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
>> -		[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
>> -		[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
>> +		[CLKID_PRIV_FIXED_PLL_DCO]	= &g12a_fixed_pll_dco.hw,
>> +		[CLKID_PRIV_SYS_PLL_DCO]	= &g12a_sys_pll_dco.hw,
>> +		[CLKID_PRIV_GP0_PLL_DCO]	= &g12a_gp0_pll_dco.hw,
>> +		[CLKID_PRIV_HIFI_PLL_DCO]	= &g12a_hifi_pll_dco.hw,
>>   		[CLKID_DMA]			= &g12a_dma.hw,
>>   		[CLKID_EFUSE]			= &g12a_efuse.hw,
>>   		[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
>>   		[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
>>   		[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
>> -		[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
>> +		[CLKID_PRIV_MPLL_PREDIV]	= &g12a_mpll_prediv.hw,
>>   		[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
>> -		[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>> +		[CLKID_PRIV_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>>   		[CLKID_VPU_0]			= &g12a_vpu_0.hw,
>>   		[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
>> -		[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>> +		[CLKID_PRIV_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>>   		[CLKID_VPU_1]			= &g12a_vpu_1.hw,
>>   		[CLKID_VPU]			= &g12a_vpu.hw,
>>   		[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
>> -		[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>> +		[CLKID_PRIV_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>>   		[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
>>   		[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
>> -		[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>> +		[CLKID_PRIV_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>>   		[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
>>   		[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
>>   		[CLKID_VAPB]			= &g12a_vapb.hw,
>> -		[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
>> -		[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
>> -		[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
>> +		[CLKID_PRIV_HDMI_PLL_DCO]	= &g12a_hdmi_pll_dco.hw,
>> +		[CLKID_PRIV_HDMI_PLL_OD]	= &g12a_hdmi_pll_od.hw,
>> +		[CLKID_PRIV_HDMI_PLL_OD2]	= &g12a_hdmi_pll_od2.hw,
>>   		[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
>>   		[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
>> -		[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
>> -		[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
>> -		[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
>> -		[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
>> -		[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
>> -		[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
>> -		[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
>> -		[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>> +		[CLKID_PRIV_VID_PLL_SEL]	= &g12a_vid_pll_sel.hw,
>> +		[CLKID_PRIV_VID_PLL_DIV]	= &g12a_vid_pll.hw,
>> +		[CLKID_PRIV_VCLK_SEL]		= &g12a_vclk_sel.hw,
>> +		[CLKID_PRIV_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
>> +		[CLKID_PRIV_VCLK_INPUT]		= &g12a_vclk_input.hw,
>> +		[CLKID_PRIV_VCLK2_INPUT]	= &g12a_vclk2_input.hw,
>> +		[CLKID_PRIV_VCLK_DIV]		= &g12a_vclk_div.hw,
>> +		[CLKID_PRIV_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>>   		[CLKID_VCLK]			= &g12a_vclk.hw,
>>   		[CLKID_VCLK2]			= &g12a_vclk2.hw,
>>   		[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
>> -		[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
>> -		[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
>> -		[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
>> -		[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
>> +		[CLKID_PRIV_VCLK_DIV2_EN]	= &g12a_vclk_div2_en.hw,
>> +		[CLKID_PRIV_VCLK_DIV4_EN]	= &g12a_vclk_div4_en.hw,
>> +		[CLKID_PRIV_VCLK_DIV6_EN]	= &g12a_vclk_div6_en.hw,
>> +		[CLKID_PRIV_VCLK_DIV12_EN]	= &g12a_vclk_div12_en.hw,
>>   		[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
>> -		[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
>> -		[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
>> -		[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
>> -		[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
>> +		[CLKID_PRIV_VCLK2_DIV2_EN]	= &g12a_vclk2_div2_en.hw,
>> +		[CLKID_PRIV_VCLK2_DIV4_EN]	= &g12a_vclk2_div4_en.hw,
>> +		[CLKID_PRIV_VCLK2_DIV6_EN]	= &g12a_vclk2_div6_en.hw,
>> +		[CLKID_PRIV_VCLK2_DIV12_EN]	= &g12a_vclk2_div12_en.hw,
>>   		[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
>>   		[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
>>   		[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
>> @@ -4633,104 +4633,104 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
>>   		[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
>>   		[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
>>   		[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
>> -		[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
>> -		[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
>> -		[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
>> -		[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
>> +		[CLKID_PRIV_CTS_ENCI_SEL]	= &g12a_cts_enci_sel.hw,
>> +		[CLKID_PRIV_CTS_ENCP_SEL]	= &g12a_cts_encp_sel.hw,
>> +		[CLKID_PRIV_CTS_VDAC_SEL]	= &g12a_cts_vdac_sel.hw,
>> +		[CLKID_PRIV_HDMI_TX_SEL]	= &g12a_hdmi_tx_sel.hw,
>>   		[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
>>   		[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
>>   		[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
>>   		[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
>> -		[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
>> -		[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
>> +		[CLKID_PRIV_HDMI_SEL]		= &g12a_hdmi_sel.hw,
>> +		[CLKID_PRIV_HDMI_DIV]		= &g12a_hdmi_div.hw,
>>   		[CLKID_HDMI]			= &g12a_hdmi.hw,
>>   		[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
>> -		[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>> +		[CLKID_PRIV_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>>   		[CLKID_MALI_0]			= &g12a_mali_0.hw,
>>   		[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
>> -		[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>> +		[CLKID_PRIV_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>>   		[CLKID_MALI_1]			= &g12a_mali_1.hw,
>>   		[CLKID_MALI]			= &g12a_mali.hw,
>> -		[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
>> +		[CLKID_PRIV_MPLL_50M_DIV]	= &g12a_mpll_50m_div.hw,
>>   		[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
>> -		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
>> -		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
>> -		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
>> -		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
>> -		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
>> -		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
>> -		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
>> -		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
>> -		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
>> +		[CLKID_PRIV_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
>> +		[CLKID_PRIV_SYS_PLL_DIV16]	= &g12a_sys_pll_div16.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN0]	= &g12a_cpu_clk_postmux0.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN1]	= &g12a_cpu_clk_postmux1.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN]	= &g12a_cpu_clk_dyn.hw,
>>   		[CLKID_CPU_CLK]			= &g12b_cpu_clk.hw,
>> -		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
>> -		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
>> -		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
>> -		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
>> -		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
>> -		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
>> -		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
>> -		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
>> -		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
>> -		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
>> -		[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
>> -		[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
>> -		[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
>> +		[CLKID_PRIV_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
>> +		[CLKID_PRIV_CPU_CLK_DIV16]	= &g12a_cpu_clk_div16.hw,
>> +		[CLKID_PRIV_CPU_CLK_APB_DIV]	= &g12a_cpu_clk_apb_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_APB]	= &g12a_cpu_clk_apb.hw,
>> +		[CLKID_PRIV_CPU_CLK_ATB_DIV]	= &g12a_cpu_clk_atb_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_ATB]	= &g12a_cpu_clk_atb.hw,
>> +		[CLKID_PRIV_CPU_CLK_AXI_DIV]	= &g12a_cpu_clk_axi_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_AXI]	= &g12a_cpu_clk_axi.hw,
>> +		[CLKID_PRIV_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_TRACE]	= &g12a_cpu_clk_trace.hw,
>> +		[CLKID_PRIV_PCIE_PLL_DCO]	= &g12a_pcie_pll_dco.hw,
>> +		[CLKID_PRIV_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
>> +		[CLKID_PRIV_PCIE_PLL_OD]	= &g12a_pcie_pll_od.hw,
>>   		[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
>> -		[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
>> -		[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>> +		[CLKID_PRIV_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
>> +		[CLKID_PRIV_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>>   		[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
>> -		[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
>> -		[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
>> +		[CLKID_PRIV_VDEC_HEVC_SEL]	= &g12a_vdec_hevc_sel.hw,
>> +		[CLKID_PRIV_VDEC_HEVC_DIV]	= &g12a_vdec_hevc_div.hw,
>>   		[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
>> -		[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
>> -		[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
>> +		[CLKID_PRIV_VDEC_HEVCF_SEL]	= &g12a_vdec_hevcf_sel.hw,
>> +		[CLKID_PRIV_VDEC_HEVCF_DIV]	= &g12a_vdec_hevcf_div.hw,
>>   		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
>> -		[CLKID_TS_DIV]			= &g12a_ts_div.hw,
>> +		[CLKID_PRIV_TS_DIV]		= &g12a_ts_div.hw,
>>   		[CLKID_TS]			= &g12a_ts.hw,
>> -		[CLKID_SYS1_PLL_DCO]		= &g12b_sys1_pll_dco.hw,
>> -		[CLKID_SYS1_PLL]		= &g12b_sys1_pll.hw,
>> -		[CLKID_SYS1_PLL_DIV16_EN]	= &g12b_sys1_pll_div16_en.hw,
>> -		[CLKID_SYS1_PLL_DIV16]		= &g12b_sys1_pll_div16.hw,
>> -		[CLKID_CPUB_CLK_DYN0_SEL]	= &g12b_cpub_clk_premux0.hw,
>> -		[CLKID_CPUB_CLK_DYN0_DIV]	= &g12b_cpub_clk_mux0_div.hw,
>> -		[CLKID_CPUB_CLK_DYN0]		= &g12b_cpub_clk_postmux0.hw,
>> -		[CLKID_CPUB_CLK_DYN1_SEL]	= &g12b_cpub_clk_premux1.hw,
>> -		[CLKID_CPUB_CLK_DYN1_DIV]	= &g12b_cpub_clk_mux1_div.hw,
>> -		[CLKID_CPUB_CLK_DYN1]		= &g12b_cpub_clk_postmux1.hw,
>> -		[CLKID_CPUB_CLK_DYN]		= &g12b_cpub_clk_dyn.hw,
>> +		[CLKID_PRIV_SYS1_PLL_DCO]	= &g12b_sys1_pll_dco.hw,
>> +		[CLKID_PRIV_SYS1_PLL]		= &g12b_sys1_pll.hw,
>> +		[CLKID_PRIV_SYS1_PLL_DIV16_EN]	= &g12b_sys1_pll_div16_en.hw,
>> +		[CLKID_PRIV_SYS1_PLL_DIV16]	= &g12b_sys1_pll_div16.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DYN0_SEL]	= &g12b_cpub_clk_premux0.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DYN0_DIV]	= &g12b_cpub_clk_mux0_div.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DYN0]	= &g12b_cpub_clk_postmux0.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DYN1_SEL]	= &g12b_cpub_clk_premux1.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DYN1_DIV]	= &g12b_cpub_clk_mux1_div.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DYN1]	= &g12b_cpub_clk_postmux1.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DYN]	= &g12b_cpub_clk_dyn.hw,
>>   		[CLKID_CPUB_CLK]		= &g12b_cpub_clk.hw,
>> -		[CLKID_CPUB_CLK_DIV16_EN]	= &g12b_cpub_clk_div16_en.hw,
>> -		[CLKID_CPUB_CLK_DIV16]		= &g12b_cpub_clk_div16.hw,
>> -		[CLKID_CPUB_CLK_DIV2]		= &g12b_cpub_clk_div2.hw,
>> -		[CLKID_CPUB_CLK_DIV3]		= &g12b_cpub_clk_div3.hw,
>> -		[CLKID_CPUB_CLK_DIV4]		= &g12b_cpub_clk_div4.hw,
>> -		[CLKID_CPUB_CLK_DIV5]		= &g12b_cpub_clk_div5.hw,
>> -		[CLKID_CPUB_CLK_DIV6]		= &g12b_cpub_clk_div6.hw,
>> -		[CLKID_CPUB_CLK_DIV7]		= &g12b_cpub_clk_div7.hw,
>> -		[CLKID_CPUB_CLK_DIV8]		= &g12b_cpub_clk_div8.hw,
>> -		[CLKID_CPUB_CLK_APB_SEL]	= &g12b_cpub_clk_apb_sel.hw,
>> -		[CLKID_CPUB_CLK_APB]		= &g12b_cpub_clk_apb.hw,
>> -		[CLKID_CPUB_CLK_ATB_SEL]	= &g12b_cpub_clk_atb_sel.hw,
>> -		[CLKID_CPUB_CLK_ATB]		= &g12b_cpub_clk_atb.hw,
>> -		[CLKID_CPUB_CLK_AXI_SEL]	= &g12b_cpub_clk_axi_sel.hw,
>> -		[CLKID_CPUB_CLK_AXI]		= &g12b_cpub_clk_axi.hw,
>> -		[CLKID_CPUB_CLK_TRACE_SEL]	= &g12b_cpub_clk_trace_sel.hw,
>> -		[CLKID_CPUB_CLK_TRACE]		= &g12b_cpub_clk_trace.hw,
>> -		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
>> -		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DIV16_EN]	= &g12b_cpub_clk_div16_en.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DIV16]	= &g12b_cpub_clk_div16.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DIV2]	= &g12b_cpub_clk_div2.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DIV3]	= &g12b_cpub_clk_div3.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DIV4]	= &g12b_cpub_clk_div4.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DIV5]	= &g12b_cpub_clk_div5.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DIV6]	= &g12b_cpub_clk_div6.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DIV7]	= &g12b_cpub_clk_div7.hw,
>> +		[CLKID_PRIV_CPUB_CLK_DIV8]	= &g12b_cpub_clk_div8.hw,
>> +		[CLKID_PRIV_CPUB_CLK_APB_SEL]	= &g12b_cpub_clk_apb_sel.hw,
>> +		[CLKID_PRIV_CPUB_CLK_APB]	= &g12b_cpub_clk_apb.hw,
>> +		[CLKID_PRIV_CPUB_CLK_ATB_SEL]	= &g12b_cpub_clk_atb_sel.hw,
>> +		[CLKID_PRIV_CPUB_CLK_ATB]	= &g12b_cpub_clk_atb.hw,
>> +		[CLKID_PRIV_CPUB_CLK_AXI_SEL]	= &g12b_cpub_clk_axi_sel.hw,
>> +		[CLKID_PRIV_CPUB_CLK_AXI]	= &g12b_cpub_clk_axi.hw,
>> +		[CLKID_PRIV_CPUB_CLK_TRACE_SEL]	= &g12b_cpub_clk_trace_sel.hw,
>> +		[CLKID_PRIV_CPUB_CLK_TRACE]	= &g12b_cpub_clk_trace.hw,
>> +		[CLKID_PRIV_SPICC0_SCLK_SEL]	= &g12a_spicc0_sclk_sel.hw,
>> +		[CLKID_PRIV_SPICC0_SCLK_DIV]	= &g12a_spicc0_sclk_div.hw,
>>   		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
>> -		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
>> -		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
>> +		[CLKID_PRIV_SPICC1_SCLK_SEL]	= &g12a_spicc1_sclk_sel.hw,
>> +		[CLKID_PRIV_SPICC1_SCLK_DIV]	= &g12a_spicc1_sclk_div.hw,
>>   		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
>> -		[CLKID_NNA_AXI_CLK_SEL]		= &sm1_nna_axi_clk_sel.hw,
>> -		[CLKID_NNA_AXI_CLK_DIV]		= &sm1_nna_axi_clk_div.hw,
>> +		[CLKID_PRIV_NNA_AXI_CLK_SEL]	= &sm1_nna_axi_clk_sel.hw,
>> +		[CLKID_PRIV_NNA_AXI_CLK_DIV]	= &sm1_nna_axi_clk_div.hw,
>>   		[CLKID_NNA_AXI_CLK]		= &sm1_nna_axi_clk.hw,
>> -		[CLKID_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
>> -		[CLKID_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
>> +		[CLKID_PRIV_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
>> +		[CLKID_PRIV_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
>>   		[CLKID_NNA_CORE_CLK]		= &sm1_nna_core_clk.hw,
>>   		[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
>> -		[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>> +		[CLKID_PRIV_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>>   		[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
>>   		[NR_CLKS]			= NULL,
>>   	},
>> @@ -4748,8 +4748,8 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
>>   		[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
>>   		[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
>>   		[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
>> -		[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
>> -		[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>> +		[CLKID_PRIV_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
>> +		[CLKID_PRIV_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>>   		[CLKID_CLK81]			= &g12a_clk81.hw,
>>   		[CLKID_MPLL0]			= &g12a_mpll0.hw,
>>   		[CLKID_MPLL1]			= &g12a_mpll1.hw,
>> @@ -4800,25 +4800,25 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
>>   		[CLKID_UART2]			= &g12a_uart2.hw,
>>   		[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
>>   		[CLKID_GIC]			= &g12a_gic.hw,
>> -		[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
>> -		[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>> +		[CLKID_PRIV_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
>> +		[CLKID_PRIV_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>>   		[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
>> -		[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
>> -		[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>> +		[CLKID_PRIV_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
>> +		[CLKID_PRIV_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>>   		[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
>> -		[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
>> -		[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>> +		[CLKID_PRIV_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
>> +		[CLKID_PRIV_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>>   		[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
>> -		[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
>> -		[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
>> -		[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
>> -		[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
>> -		[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
>> -		[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
>> -		[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
>> -		[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
>> -		[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
>> -		[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
>> +		[CLKID_PRIV_MPLL0_DIV]		= &g12a_mpll0_div.hw,
>> +		[CLKID_PRIV_MPLL1_DIV]		= &g12a_mpll1_div.hw,
>> +		[CLKID_PRIV_MPLL2_DIV]		= &g12a_mpll2_div.hw,
>> +		[CLKID_PRIV_MPLL3_DIV]		= &g12a_mpll3_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV2_DIV]	= &g12a_fclk_div2_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV3_DIV]	= &g12a_fclk_div3_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV4_DIV]	= &g12a_fclk_div4_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV5_DIV]	= &g12a_fclk_div5_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV7_DIV]	= &g12a_fclk_div7_div.hw,
>> +		[CLKID_PRIV_FCLK_DIV2P5_DIV]	= &g12a_fclk_div2p5_div.hw,
>>   		[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
>>   		[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
>>   		[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
>> @@ -4839,56 +4839,56 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
>>   		[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
>>   		[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
>>   		[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
>> -		[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
>> -		[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
>> -		[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
>> -		[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
>> +		[CLKID_PRIV_FIXED_PLL_DCO]	= &g12a_fixed_pll_dco.hw,
>> +		[CLKID_PRIV_SYS_PLL_DCO]	= &g12a_sys_pll_dco.hw,
>> +		[CLKID_PRIV_GP0_PLL_DCO]	= &g12a_gp0_pll_dco.hw,
>> +		[CLKID_PRIV_HIFI_PLL_DCO]	= &g12a_hifi_pll_dco.hw,
>>   		[CLKID_DMA]			= &g12a_dma.hw,
>>   		[CLKID_EFUSE]			= &g12a_efuse.hw,
>>   		[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
>>   		[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
>>   		[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
>> -		[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
>> +		[CLKID_PRIV_MPLL_PREDIV]	= &g12a_mpll_prediv.hw,
>>   		[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
>> -		[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>> +		[CLKID_PRIV_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>>   		[CLKID_VPU_0]			= &g12a_vpu_0.hw,
>>   		[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
>> -		[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>> +		[CLKID_PRIV_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>>   		[CLKID_VPU_1]			= &g12a_vpu_1.hw,
>>   		[CLKID_VPU]			= &g12a_vpu.hw,
>>   		[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
>> -		[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>> +		[CLKID_PRIV_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>>   		[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
>>   		[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
>> -		[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>> +		[CLKID_PRIV_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>>   		[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
>>   		[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
>>   		[CLKID_VAPB]			= &g12a_vapb.hw,
>> -		[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
>> -		[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
>> -		[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
>> +		[CLKID_PRIV_HDMI_PLL_DCO]	= &g12a_hdmi_pll_dco.hw,
>> +		[CLKID_PRIV_HDMI_PLL_OD]	= &g12a_hdmi_pll_od.hw,
>> +		[CLKID_PRIV_HDMI_PLL_OD2]	= &g12a_hdmi_pll_od2.hw,
>>   		[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
>>   		[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
>> -		[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
>> -		[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
>> -		[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
>> -		[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
>> -		[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
>> -		[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
>> -		[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
>> -		[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>> +		[CLKID_PRIV_VID_PLL_SEL]	= &g12a_vid_pll_sel.hw,
>> +		[CLKID_PRIV_VID_PLL_DIV]	= &g12a_vid_pll.hw,
>> +		[CLKID_PRIV_VCLK_SEL]		= &g12a_vclk_sel.hw,
>> +		[CLKID_PRIV_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
>> +		[CLKID_PRIV_VCLK_INPUT]		= &g12a_vclk_input.hw,
>> +		[CLKID_PRIV_VCLK2_INPUT]	= &g12a_vclk2_input.hw,
>> +		[CLKID_PRIV_VCLK_DIV]		= &g12a_vclk_div.hw,
>> +		[CLKID_PRIV_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>>   		[CLKID_VCLK]			= &g12a_vclk.hw,
>>   		[CLKID_VCLK2]			= &g12a_vclk2.hw,
>>   		[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
>> -		[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
>> -		[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
>> -		[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
>> -		[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
>> +		[CLKID_PRIV_VCLK_DIV2_EN]	= &g12a_vclk_div2_en.hw,
>> +		[CLKID_PRIV_VCLK_DIV4_EN]	= &g12a_vclk_div4_en.hw,
>> +		[CLKID_PRIV_VCLK_DIV6_EN]	= &g12a_vclk_div6_en.hw,
>> +		[CLKID_PRIV_VCLK_DIV12_EN]	= &g12a_vclk_div12_en.hw,
>>   		[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
>> -		[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
>> -		[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
>> -		[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
>> -		[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
>> +		[CLKID_PRIV_VCLK2_DIV2_EN]	= &g12a_vclk2_div2_en.hw,
>> +		[CLKID_PRIV_VCLK2_DIV4_EN]	= &g12a_vclk2_div4_en.hw,
>> +		[CLKID_PRIV_VCLK2_DIV6_EN]	= &g12a_vclk2_div6_en.hw,
>> +		[CLKID_PRIV_VCLK2_DIV12_EN]	= &g12a_vclk2_div12_en.hw,
>>   		[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
>>   		[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
>>   		[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
>> @@ -4897,89 +4897,89 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
>>   		[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
>>   		[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
>>   		[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
>> -		[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
>> -		[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
>> -		[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
>> -		[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
>> +		[CLKID_PRIV_CTS_ENCI_SEL]	= &g12a_cts_enci_sel.hw,
>> +		[CLKID_PRIV_CTS_ENCP_SEL]	= &g12a_cts_encp_sel.hw,
>> +		[CLKID_PRIV_CTS_VDAC_SEL]	= &g12a_cts_vdac_sel.hw,
>> +		[CLKID_PRIV_HDMI_TX_SEL]	= &g12a_hdmi_tx_sel.hw,
>>   		[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
>>   		[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
>>   		[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
>>   		[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
>> -		[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
>> -		[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
>> +		[CLKID_PRIV_HDMI_SEL]		= &g12a_hdmi_sel.hw,
>> +		[CLKID_PRIV_HDMI_DIV]		= &g12a_hdmi_div.hw,
>>   		[CLKID_HDMI]			= &g12a_hdmi.hw,
>>   		[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
>> -		[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>> +		[CLKID_PRIV_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>>   		[CLKID_MALI_0]			= &g12a_mali_0.hw,
>>   		[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
>> -		[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>> +		[CLKID_PRIV_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>>   		[CLKID_MALI_1]			= &g12a_mali_1.hw,
>>   		[CLKID_MALI]			= &g12a_mali.hw,
>> -		[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
>> +		[CLKID_PRIV_MPLL_50M_DIV]	= &g12a_mpll_50m_div.hw,
>>   		[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
>> -		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
>> -		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
>> -		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
>> -		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
>> -		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
>> -		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
>> -		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
>> -		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
>> -		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
>> +		[CLKID_PRIV_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
>> +		[CLKID_PRIV_SYS_PLL_DIV16]	= &g12a_sys_pll_div16.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN0]	= &g12a_cpu_clk_postmux0.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN1]	= &g12a_cpu_clk_postmux1.hw,
>> +		[CLKID_PRIV_CPU_CLK_DYN]	= &g12a_cpu_clk_dyn.hw,
>>   		[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,
>> -		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
>> -		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
>> -		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
>> -		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
>> -		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
>> -		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
>> -		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
>> -		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
>> -		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
>> -		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
>> -		[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
>> -		[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
>> -		[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
>> +		[CLKID_PRIV_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
>> +		[CLKID_PRIV_CPU_CLK_DIV16]	= &g12a_cpu_clk_div16.hw,
>> +		[CLKID_PRIV_CPU_CLK_APB_DIV]	= &g12a_cpu_clk_apb_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_APB]	= &g12a_cpu_clk_apb.hw,
>> +		[CLKID_PRIV_CPU_CLK_ATB_DIV]	= &g12a_cpu_clk_atb_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_ATB]	= &g12a_cpu_clk_atb.hw,
>> +		[CLKID_PRIV_CPU_CLK_AXI_DIV]	= &g12a_cpu_clk_axi_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_AXI]	= &g12a_cpu_clk_axi.hw,
>> +		[CLKID_PRIV_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
>> +		[CLKID_PRIV_CPU_CLK_TRACE]	= &g12a_cpu_clk_trace.hw,
>> +		[CLKID_PRIV_PCIE_PLL_DCO]	= &g12a_pcie_pll_dco.hw,
>> +		[CLKID_PRIV_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
>> +		[CLKID_PRIV_PCIE_PLL_OD]	= &g12a_pcie_pll_od.hw,
>>   		[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
>> -		[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
>> -		[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>> +		[CLKID_PRIV_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
>> +		[CLKID_PRIV_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>>   		[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
>> -		[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
>> -		[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
>> +		[CLKID_PRIV_VDEC_HEVC_SEL]	= &g12a_vdec_hevc_sel.hw,
>> +		[CLKID_PRIV_VDEC_HEVC_DIV]	= &g12a_vdec_hevc_div.hw,
>>   		[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
>> -		[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
>> -		[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
>> +		[CLKID_PRIV_VDEC_HEVCF_SEL]	= &g12a_vdec_hevcf_sel.hw,
>> +		[CLKID_PRIV_VDEC_HEVCF_DIV]	= &g12a_vdec_hevcf_div.hw,
>>   		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
>> -		[CLKID_TS_DIV]			= &g12a_ts_div.hw,
>> +		[CLKID_PRIV_TS_DIV]		= &g12a_ts_div.hw,
>>   		[CLKID_TS]			= &g12a_ts.hw,
>> -		[CLKID_GP1_PLL_DCO]		= &sm1_gp1_pll_dco.hw,
>> +		[CLKID_PRIV_GP1_PLL_DCO]	= &sm1_gp1_pll_dco.hw,
>>   		[CLKID_GP1_PLL]			= &sm1_gp1_pll.hw,
>> -		[CLKID_DSU_CLK_DYN0_SEL]	= &sm1_dsu_clk_premux0.hw,
>> -		[CLKID_DSU_CLK_DYN0_DIV]	= &sm1_dsu_clk_premux1.hw,
>> -		[CLKID_DSU_CLK_DYN0]		= &sm1_dsu_clk_mux0_div.hw,
>> -		[CLKID_DSU_CLK_DYN1_SEL]	= &sm1_dsu_clk_postmux0.hw,
>> -		[CLKID_DSU_CLK_DYN1_DIV]	= &sm1_dsu_clk_mux1_div.hw,
>> -		[CLKID_DSU_CLK_DYN1]		= &sm1_dsu_clk_postmux1.hw,
>> -		[CLKID_DSU_CLK_DYN]		= &sm1_dsu_clk_dyn.hw,
>> -		[CLKID_DSU_CLK_FINAL]		= &sm1_dsu_final_clk.hw,
>> +		[CLKID_PRIV_DSU_CLK_DYN0_SEL]	= &sm1_dsu_clk_premux0.hw,
>> +		[CLKID_PRIV_DSU_CLK_DYN0_DIV]	= &sm1_dsu_clk_premux1.hw,
>> +		[CLKID_PRIV_DSU_CLK_DYN0]	= &sm1_dsu_clk_mux0_div.hw,
>> +		[CLKID_PRIV_DSU_CLK_DYN1_SEL]	= &sm1_dsu_clk_postmux0.hw,
>> +		[CLKID_PRIV_DSU_CLK_DYN1_DIV]	= &sm1_dsu_clk_mux1_div.hw,
>> +		[CLKID_PRIV_DSU_CLK_DYN1]	= &sm1_dsu_clk_postmux1.hw,
>> +		[CLKID_PRIV_DSU_CLK_DYN]	= &sm1_dsu_clk_dyn.hw,
>> +		[CLKID_PRIV_DSU_CLK_FINAL]	= &sm1_dsu_final_clk.hw,
>>   		[CLKID_DSU_CLK]			= &sm1_dsu_clk.hw,
>>   		[CLKID_CPU1_CLK]		= &sm1_cpu1_clk.hw,
>>   		[CLKID_CPU2_CLK]		= &sm1_cpu2_clk.hw,
>>   		[CLKID_CPU3_CLK]		= &sm1_cpu3_clk.hw,
>> -		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
>> -		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
>> +		[CLKID_PRIV_SPICC0_SCLK_SEL]	= &g12a_spicc0_sclk_sel.hw,
>> +		[CLKID_PRIV_SPICC0_SCLK_DIV]	= &g12a_spicc0_sclk_div.hw,
>>   		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
>> -		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
>> -		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
>> +		[CLKID_PRIV_SPICC1_SCLK_SEL]	= &g12a_spicc1_sclk_sel.hw,
>> +		[CLKID_PRIV_SPICC1_SCLK_DIV]	= &g12a_spicc1_sclk_div.hw,
>>   		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
>> -		[CLKID_NNA_AXI_CLK_SEL]		= &sm1_nna_axi_clk_sel.hw,
>> -		[CLKID_NNA_AXI_CLK_DIV]		= &sm1_nna_axi_clk_div.hw,
>> +		[CLKID_PRIV_NNA_AXI_CLK_SEL]	= &sm1_nna_axi_clk_sel.hw,
>> +		[CLKID_PRIV_NNA_AXI_CLK_DIV]	= &sm1_nna_axi_clk_div.hw,
>>   		[CLKID_NNA_AXI_CLK]		= &sm1_nna_axi_clk.hw,
>> -		[CLKID_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
>> -		[CLKID_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
>> +		[CLKID_PRIV_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
>> +		[CLKID_PRIV_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
>>   		[CLKID_NNA_CORE_CLK]		= &sm1_nna_core_clk.hw,
>>   		[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
>> -		[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>> +		[CLKID_PRIV_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>>   		[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
>>   		[NR_CLKS]			= NULL,
>>   	},
>> @@ -5246,7 +5246,7 @@ static int meson_g12a_dvfs_setup_common(struct device *dev,
>>   	struct clk_hw *xtal;
>>   	int ret;
>>   
>> -	xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
>> +	xtal = clk_hw_get_parent_by_index(hws[CLKID_PRIV_CPU_CLK_DYN1_SEL], 0);
>>   
>>   	/* Setup clock notifier for cpu_clk_postmux0 */
>>   	g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
>> @@ -5284,7 +5284,7 @@ static int meson_g12b_dvfs_setup(struct platform_device *pdev)
>>   	if (ret)
>>   		return ret;
>>   
>> -	xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
>> +	xtal = clk_hw_get_parent_by_index(hws[CLKID_PRIV_CPU_CLK_DYN1_SEL], 0);
>>   
>>   	/* Setup clock notifier for cpu_clk mux */
>>   	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw,
>> diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
>> index a97613df38b3..a57f4a9717db 100644
>> --- a/drivers/clk/meson/g12a.h
>> +++ b/drivers/clk/meson/g12a.h
>> @@ -135,136 +135,136 @@
>>    * to expose, such as the internal muxes and dividers of composite clocks,
>>    * will remain defined here.
>>    */
>> -#define CLKID_MPEG_SEL				8
>> -#define CLKID_MPEG_DIV				9
>> -#define CLKID_SD_EMMC_A_CLK0_SEL		63
>> -#define CLKID_SD_EMMC_A_CLK0_DIV		64
>> -#define CLKID_SD_EMMC_B_CLK0_SEL		65
>> -#define CLKID_SD_EMMC_B_CLK0_DIV		66
>> -#define CLKID_SD_EMMC_C_CLK0_SEL		67
>> -#define CLKID_SD_EMMC_C_CLK0_DIV		68
>> -#define CLKID_MPLL0_DIV				69
>> -#define CLKID_MPLL1_DIV				70
>> -#define CLKID_MPLL2_DIV				71
>> -#define CLKID_MPLL3_DIV				72
>> -#define CLKID_MPLL_PREDIV			73
>> -#define CLKID_FCLK_DIV2_DIV			75
>> -#define CLKID_FCLK_DIV3_DIV			76
>> -#define CLKID_FCLK_DIV4_DIV			77
>> -#define CLKID_FCLK_DIV5_DIV			78
>> -#define CLKID_FCLK_DIV7_DIV			79
>> -#define CLKID_FCLK_DIV2P5_DIV			100
>> -#define CLKID_FIXED_PLL_DCO			101
>> -#define CLKID_SYS_PLL_DCO			102
>> -#define CLKID_GP0_PLL_DCO			103
>> -#define CLKID_HIFI_PLL_DCO			104
>> -#define CLKID_VPU_0_DIV				111
>> -#define CLKID_VPU_1_DIV				114
>> -#define CLKID_VAPB_0_DIV			118
>> -#define CLKID_VAPB_1_DIV			121
>> -#define CLKID_HDMI_PLL_DCO			125
>> -#define CLKID_HDMI_PLL_OD			126
>> -#define CLKID_HDMI_PLL_OD2			127
>> -#define CLKID_VID_PLL_SEL			130
>> -#define CLKID_VID_PLL_DIV			131
>> -#define CLKID_VCLK_SEL				132
>> -#define CLKID_VCLK2_SEL				133
>> -#define CLKID_VCLK_INPUT			134
>> -#define CLKID_VCLK2_INPUT			135
>> -#define CLKID_VCLK_DIV				136
>> -#define CLKID_VCLK2_DIV				137
>> -#define CLKID_VCLK_DIV2_EN			140
>> -#define CLKID_VCLK_DIV4_EN			141
>> -#define CLKID_VCLK_DIV6_EN			142
>> -#define CLKID_VCLK_DIV12_EN			143
>> -#define CLKID_VCLK2_DIV2_EN			144
>> -#define CLKID_VCLK2_DIV4_EN			145
>> -#define CLKID_VCLK2_DIV6_EN			146
>> -#define CLKID_VCLK2_DIV12_EN			147
>> -#define CLKID_CTS_ENCI_SEL			158
>> -#define CLKID_CTS_ENCP_SEL			159
>> -#define CLKID_CTS_VDAC_SEL			160
>> -#define CLKID_HDMI_TX_SEL			161
>> -#define CLKID_HDMI_SEL				166
>> -#define CLKID_HDMI_DIV				167
>> -#define CLKID_MALI_0_DIV			170
>> -#define CLKID_MALI_1_DIV			173
>> -#define CLKID_MPLL_50M_DIV			176
>> -#define CLKID_SYS_PLL_DIV16_EN			178
>> -#define CLKID_SYS_PLL_DIV16			179
>> -#define CLKID_CPU_CLK_DYN0_SEL			180
>> -#define CLKID_CPU_CLK_DYN0_DIV			181
>> -#define CLKID_CPU_CLK_DYN0			182
>> -#define CLKID_CPU_CLK_DYN1_SEL			183
>> -#define CLKID_CPU_CLK_DYN1_DIV			184
>> -#define CLKID_CPU_CLK_DYN1			185
>> -#define CLKID_CPU_CLK_DYN			186
>> -#define CLKID_CPU_CLK_DIV16_EN			188
>> -#define CLKID_CPU_CLK_DIV16			189
>> -#define CLKID_CPU_CLK_APB_DIV			190
>> -#define CLKID_CPU_CLK_APB			191
>> -#define CLKID_CPU_CLK_ATB_DIV			192
>> -#define CLKID_CPU_CLK_ATB			193
>> -#define CLKID_CPU_CLK_AXI_DIV			194
>> -#define CLKID_CPU_CLK_AXI			195
>> -#define CLKID_CPU_CLK_TRACE_DIV			196
>> -#define CLKID_CPU_CLK_TRACE			197
>> -#define CLKID_PCIE_PLL_DCO			198
>> -#define CLKID_PCIE_PLL_DCO_DIV2			199
>> -#define CLKID_PCIE_PLL_OD			200
>> -#define CLKID_VDEC_1_SEL			202
>> -#define CLKID_VDEC_1_DIV			203
>> -#define CLKID_VDEC_HEVC_SEL			205
>> -#define CLKID_VDEC_HEVC_DIV			206
>> -#define CLKID_VDEC_HEVCF_SEL			208
>> -#define CLKID_VDEC_HEVCF_DIV			209
>> -#define CLKID_TS_DIV				211
>> -#define CLKID_SYS1_PLL_DCO			213
>> -#define CLKID_SYS1_PLL				214
>> -#define CLKID_SYS1_PLL_DIV16_EN			215
>> -#define CLKID_SYS1_PLL_DIV16			216
>> -#define CLKID_CPUB_CLK_DYN0_SEL			217
>> -#define CLKID_CPUB_CLK_DYN0_DIV			218
>> -#define CLKID_CPUB_CLK_DYN0			219
>> -#define CLKID_CPUB_CLK_DYN1_SEL			220
>> -#define CLKID_CPUB_CLK_DYN1_DIV			221
>> -#define CLKID_CPUB_CLK_DYN1			222
>> -#define CLKID_CPUB_CLK_DYN			223
>> -#define CLKID_CPUB_CLK_DIV16_EN			225
>> -#define CLKID_CPUB_CLK_DIV16			226
>> -#define CLKID_CPUB_CLK_DIV2			227
>> -#define CLKID_CPUB_CLK_DIV3			228
>> -#define CLKID_CPUB_CLK_DIV4			229
>> -#define CLKID_CPUB_CLK_DIV5			230
>> -#define CLKID_CPUB_CLK_DIV6			231
>> -#define CLKID_CPUB_CLK_DIV7			232
>> -#define CLKID_CPUB_CLK_DIV8			233
>> -#define CLKID_CPUB_CLK_APB_SEL			234
>> -#define CLKID_CPUB_CLK_APB			235
>> -#define CLKID_CPUB_CLK_ATB_SEL			236
>> -#define CLKID_CPUB_CLK_ATB			237
>> -#define CLKID_CPUB_CLK_AXI_SEL			238
>> -#define CLKID_CPUB_CLK_AXI			239
>> -#define CLKID_CPUB_CLK_TRACE_SEL		240
>> -#define CLKID_CPUB_CLK_TRACE			241
>> -#define CLKID_GP1_PLL_DCO			242
>> -#define CLKID_DSU_CLK_DYN0_SEL			244
>> -#define CLKID_DSU_CLK_DYN0_DIV			245
>> -#define CLKID_DSU_CLK_DYN0			246
>> -#define CLKID_DSU_CLK_DYN1_SEL			247
>> -#define CLKID_DSU_CLK_DYN1_DIV			248
>> -#define CLKID_DSU_CLK_DYN1			249
>> -#define CLKID_DSU_CLK_DYN			250
>> -#define CLKID_DSU_CLK_FINAL			251
>> -#define CLKID_SPICC0_SCLK_SEL			256
>> -#define CLKID_SPICC0_SCLK_DIV			257
>> -#define CLKID_SPICC1_SCLK_SEL			259
>> -#define CLKID_SPICC1_SCLK_DIV			260
>> -#define CLKID_NNA_AXI_CLK_SEL			262
>> -#define CLKID_NNA_AXI_CLK_DIV			263
>> -#define CLKID_NNA_CORE_CLK_SEL			265
>> -#define CLKID_NNA_CORE_CLK_DIV			266
>> -#define CLKID_MIPI_DSI_PXCLK_DIV		268
>> +#define CLKID_PRIV_MPEG_SEL			8
>> +#define CLKID_PRIV_MPEG_DIV			9
>> +#define CLKID_PRIV_SD_EMMC_A_CLK0_SEL		63
>> +#define CLKID_PRIV_SD_EMMC_A_CLK0_DIV		64
>> +#define CLKID_PRIV_SD_EMMC_B_CLK0_SEL		65
>> +#define CLKID_PRIV_SD_EMMC_B_CLK0_DIV		66
>> +#define CLKID_PRIV_SD_EMMC_C_CLK0_SEL		67
>> +#define CLKID_PRIV_SD_EMMC_C_CLK0_DIV		68
>> +#define CLKID_PRIV_MPLL0_DIV			69
>> +#define CLKID_PRIV_MPLL1_DIV			70
>> +#define CLKID_PRIV_MPLL2_DIV			71
>> +#define CLKID_PRIV_MPLL3_DIV			72
>> +#define CLKID_PRIV_MPLL_PREDIV			73
>> +#define CLKID_PRIV_FCLK_DIV2_DIV		75
>> +#define CLKID_PRIV_FCLK_DIV3_DIV		76
>> +#define CLKID_PRIV_FCLK_DIV4_DIV		77
>> +#define CLKID_PRIV_FCLK_DIV5_DIV		78
>> +#define CLKID_PRIV_FCLK_DIV7_DIV		79
>> +#define CLKID_PRIV_FCLK_DIV2P5_DIV		100
>> +#define CLKID_PRIV_FIXED_PLL_DCO		101
>> +#define CLKID_PRIV_SYS_PLL_DCO			102
>> +#define CLKID_PRIV_GP0_PLL_DCO			103
>> +#define CLKID_PRIV_HIFI_PLL_DCO			104
>> +#define CLKID_PRIV_VPU_0_DIV			111
>> +#define CLKID_PRIV_VPU_1_DIV			114
>> +#define CLKID_PRIV_VAPB_0_DIV			118
>> +#define CLKID_PRIV_VAPB_1_DIV			121
>> +#define CLKID_PRIV_HDMI_PLL_DCO			125
>> +#define CLKID_PRIV_HDMI_PLL_OD			126
>> +#define CLKID_PRIV_HDMI_PLL_OD2			127
>> +#define CLKID_PRIV_VID_PLL_SEL			130
>> +#define CLKID_PRIV_VID_PLL_DIV			131
>> +#define CLKID_PRIV_VCLK_SEL			132
>> +#define CLKID_PRIV_VCLK2_SEL			133
>> +#define CLKID_PRIV_VCLK_INPUT			134
>> +#define CLKID_PRIV_VCLK2_INPUT			135
>> +#define CLKID_PRIV_VCLK_DIV			136
>> +#define CLKID_PRIV_VCLK2_DIV			137
>> +#define CLKID_PRIV_VCLK_DIV2_EN			140
>> +#define CLKID_PRIV_VCLK_DIV4_EN			141
>> +#define CLKID_PRIV_VCLK_DIV6_EN			142
>> +#define CLKID_PRIV_VCLK_DIV12_EN		143
>> +#define CLKID_PRIV_VCLK2_DIV2_EN		144
>> +#define CLKID_PRIV_VCLK2_DIV4_EN		145
>> +#define CLKID_PRIV_VCLK2_DIV6_EN		146
>> +#define CLKID_PRIV_VCLK2_DIV12_EN		147
>> +#define CLKID_PRIV_CTS_ENCI_SEL			158
>> +#define CLKID_PRIV_CTS_ENCP_SEL			159
>> +#define CLKID_PRIV_CTS_VDAC_SEL			160
>> +#define CLKID_PRIV_HDMI_TX_SEL			161
>> +#define CLKID_PRIV_HDMI_SEL			166
>> +#define CLKID_PRIV_HDMI_DIV			167
>> +#define CLKID_PRIV_MALI_0_DIV			170
>> +#define CLKID_PRIV_MALI_1_DIV			173
>> +#define CLKID_PRIV_MPLL_50M_DIV			176
>> +#define CLKID_PRIV_SYS_PLL_DIV16_EN		178
>> +#define CLKID_PRIV_SYS_PLL_DIV16		179
>> +#define CLKID_PRIV_CPU_CLK_DYN0_SEL		180
>> +#define CLKID_PRIV_CPU_CLK_DYN0_DIV		181
>> +#define CLKID_PRIV_CPU_CLK_DYN0			182
>> +#define CLKID_PRIV_CPU_CLK_DYN1_SEL		183
>> +#define CLKID_PRIV_CPU_CLK_DYN1_DIV		184
>> +#define CLKID_PRIV_CPU_CLK_DYN1			185
>> +#define CLKID_PRIV_CPU_CLK_DYN			186
>> +#define CLKID_PRIV_CPU_CLK_DIV16_EN		188
>> +#define CLKID_PRIV_CPU_CLK_DIV16		189
>> +#define CLKID_PRIV_CPU_CLK_APB_DIV		190
>> +#define CLKID_PRIV_CPU_CLK_APB			191
>> +#define CLKID_PRIV_CPU_CLK_ATB_DIV		192
>> +#define CLKID_PRIV_CPU_CLK_ATB			193
>> +#define CLKID_PRIV_CPU_CLK_AXI_DIV		194
>> +#define CLKID_PRIV_CPU_CLK_AXI			195
>> +#define CLKID_PRIV_CPU_CLK_TRACE_DIV		196
>> +#define CLKID_PRIV_CPU_CLK_TRACE		197
>> +#define CLKID_PRIV_PCIE_PLL_DCO			198
>> +#define CLKID_PRIV_PCIE_PLL_DCO_DIV2		199
>> +#define CLKID_PRIV_PCIE_PLL_OD			200
>> +#define CLKID_PRIV_VDEC_1_SEL			202
>> +#define CLKID_PRIV_VDEC_1_DIV			203
>> +#define CLKID_PRIV_VDEC_HEVC_SEL		205
>> +#define CLKID_PRIV_VDEC_HEVC_DIV		206
>> +#define CLKID_PRIV_VDEC_HEVCF_SEL		208
>> +#define CLKID_PRIV_VDEC_HEVCF_DIV		209
>> +#define CLKID_PRIV_TS_DIV			211
>> +#define CLKID_PRIV_SYS1_PLL_DCO			213
>> +#define CLKID_PRIV_SYS1_PLL			214
>> +#define CLKID_PRIV_SYS1_PLL_DIV16_EN		215
>> +#define CLKID_PRIV_SYS1_PLL_DIV16		216
>> +#define CLKID_PRIV_CPUB_CLK_DYN0_SEL		217
>> +#define CLKID_PRIV_CPUB_CLK_DYN0_DIV		218
>> +#define CLKID_PRIV_CPUB_CLK_DYN0		219
>> +#define CLKID_PRIV_CPUB_CLK_DYN1_SEL		220
>> +#define CLKID_PRIV_CPUB_CLK_DYN1_DIV		221
>> +#define CLKID_PRIV_CPUB_CLK_DYN1		222
>> +#define CLKID_PRIV_CPUB_CLK_DYN			223
>> +#define CLKID_PRIV_CPUB_CLK_DIV16_EN		225
>> +#define CLKID_PRIV_CPUB_CLK_DIV16		226
>> +#define CLKID_PRIV_CPUB_CLK_DIV2		227
>> +#define CLKID_PRIV_CPUB_CLK_DIV3		228
>> +#define CLKID_PRIV_CPUB_CLK_DIV4		229
>> +#define CLKID_PRIV_CPUB_CLK_DIV5		230
>> +#define CLKID_PRIV_CPUB_CLK_DIV6		231
>> +#define CLKID_PRIV_CPUB_CLK_DIV7		232
>> +#define CLKID_PRIV_CPUB_CLK_DIV8		233
>> +#define CLKID_PRIV_CPUB_CLK_APB_SEL		234
>> +#define CLKID_PRIV_CPUB_CLK_APB			235
>> +#define CLKID_PRIV_CPUB_CLK_ATB_SEL		236
>> +#define CLKID_PRIV_CPUB_CLK_ATB			237
>> +#define CLKID_PRIV_CPUB_CLK_AXI_SEL		238
>> +#define CLKID_PRIV_CPUB_CLK_AXI			239
>> +#define CLKID_PRIV_CPUB_CLK_TRACE_SEL		240
>> +#define CLKID_PRIV_CPUB_CLK_TRACE		241
>> +#define CLKID_PRIV_GP1_PLL_DCO			242
>> +#define CLKID_PRIV_DSU_CLK_DYN0_SEL		244
>> +#define CLKID_PRIV_DSU_CLK_DYN0_DIV		245
>> +#define CLKID_PRIV_DSU_CLK_DYN0			246
>> +#define CLKID_PRIV_DSU_CLK_DYN1_SEL		247
>> +#define CLKID_PRIV_DSU_CLK_DYN1_DIV		248
>> +#define CLKID_PRIV_DSU_CLK_DYN1			249
>> +#define CLKID_PRIV_DSU_CLK_DYN			250
>> +#define CLKID_PRIV_DSU_CLK_FINAL		251
>> +#define CLKID_PRIV_SPICC0_SCLK_SEL		256
>> +#define CLKID_PRIV_SPICC0_SCLK_DIV		257
>> +#define CLKID_PRIV_SPICC1_SCLK_SEL		259
>> +#define CLKID_PRIV_SPICC1_SCLK_DIV		260
>> +#define CLKID_PRIV_NNA_AXI_CLK_SEL		262
>> +#define CLKID_PRIV_NNA_AXI_CLK_DIV		263
>> +#define CLKID_PRIV_NNA_CORE_CLK_SEL		265
>> +#define CLKID_PRIV_NNA_CORE_CLK_DIV		266
>> +#define CLKID_PRIV_MIPI_DSI_PXCLK_DIV		268
>>   
>>   #define NR_CLKS					271
>

Neil Armstrong May 30, 2023, 3:57 p.m. UTC | #4

On 30/05/2023 10:14, Jerome Brunet wrote:
> 
> On Tue 30 May 2023 at 09:38, Neil Armstrong <[e-mail]> wrote:
> 
>> In order to setup the DSI clock, let's make the unused VCLK2 clock path
>> configuration via CCF.
>>
>> The nocache option is removed from following clocks:
>> - vclk2_sel
>> - vclk2_input
>> - vclk2_div
>> - vclk2
>> - vclk_div1
>> - vclk2_div2_en
>> - vclk2_div4_en
>> - vclk2_div6_en
>> - vclk2_div12_en
>> - vclk2_div2
>> - vclk2_div4
>> - vclk2_div6
>> - vclk2_div12
>> - cts_encl_sel
>>
>> The missing vclk2 reset sequence is handled via new clkc notifiers
>> in order to reset the vclk2 after each rate change as done by Amlogic
>> in the vendor implementation.
>>
>> In order to set a rate on cts_encl via the vclk2 clock path,
>> the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order
>> to keep CCF from selection a parent.
>> The parents of cts_encl_sel & vclk2_sel are expected to be defined
>> in DT.
>>
>> The following clock scheme is to be used for DSI:
>>
>> xtal
>> \_ gp0_pll_dco
>>     \_ gp0_pll
>>        |- vclk2_sel
>>        |  \_ vclk2_input
>>        |     \_ vclk2_div
>>        |        \_ vclk2
>>        |           \_ vclk2_div1
>>        |              \_ cts_encl_sel
>>        |                 \_ cts_encl	-> to VPU LCD Encoder
>>        |- mipi_dsi_pxclk_sel
>>        \_ mipi_dsi_pxclk_div
>>           \_ mipi_dsi_pxclk		-> to DSI controller
>>
>> The mipi_dsi_pxclk_div is set as RO in order to use the same GP0
>> for mipi_dsi_pxclk and vclk2_input.
> 
> I don't think notifiers is the appropriate approach here.
> Whenever there is clock change the motifiers would trigger an off/on of
> the clock, regardless of the clock usage or state.
> If you have several consummers on this vclk2, this would
> cause glitches and maybe this is not desirable.
> 
> I think it would be better to handle the enable and reset with a
> specific gate driver, in prepare() or enable(), and the give the clock
> CLK_SET_RATE_GATE flag.
> 
> This would require the clock to be properly turn off before changing the
> rate.

Sure, will see how to switch to that, seem Martin did than on Meson8.

Neil

> 
>>
>> Signed-off-by: Neil Armstrong <[e-mail]>
>> ---
>>   drivers/clk/meson/g12a.c | 131 +++++++++++++++++++++++++++++++++++++++++++----
>>   1 file changed, 120 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
>> index 461ebd79497c..e4053f4957d5 100644
>> --- a/drivers/clk/meson/g12a.c
>> +++ b/drivers/clk/meson/g12a.c
>> @@ -3163,7 +3163,7 @@ static struct clk_regmap g12a_vclk2_sel = {
>>   		.ops = &clk_regmap_mux_ops,
>>   		.parent_hws = g12a_vclk_parent_hws,
>>   		.num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
>> -		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
>> +		.flags = CLK_SET_RATE_NO_REPARENT,
>>   	},
>>   };
>>   
>> @@ -3191,7 +3191,6 @@ static struct clk_regmap g12a_vclk2_input = {
>>   		.ops = &clk_regmap_gate_ops,
>>   		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
>>   		.num_parents = 1,
>> -		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>>   	},
>>   };
>>   
>> @@ -3212,6 +3211,40 @@ static struct clk_regmap g12a_vclk_div = {
>>   	},
>>   };
>>   
>> +struct g12a_vclk_div_notifier {
>> +	struct clk_regmap *clk;
>> +	unsigned int offset;
>> +	u8 en_bit_idx;
>> +	u8 reset_bit_idx;
>> +	struct notifier_block nb;
>> +};
>> +
>> +static int g12a_vclk_div_notifier_cb(struct notifier_block *nb,
>> +				  unsigned long event, void *data)
>> +{
>> +	struct g12a_vclk_div_notifier *nb_data =
>> +		container_of(nb, struct g12a_vclk_div_notifier, nb);
>> +
>> +	switch (event) {
>> +	case PRE_RATE_CHANGE:
>> +		/* disable and reset vclk2 divider */
>> +		regmap_update_bits(nb_data->clk->map, nb_data->offset,
>> +				   BIT(nb_data->en_bit_idx) |
>> +				   BIT(nb_data->reset_bit_idx),
>> +				   BIT(nb_data->reset_bit_idx));
>> +		return NOTIFY_OK;
>> +	case POST_RATE_CHANGE:
>> +		/* enabled and release reset */
>> +		regmap_update_bits(nb_data->clk->map, nb_data->offset,
>> +				   BIT(nb_data->en_bit_idx) |
>> +				   BIT(nb_data->reset_bit_idx),
>> +				   BIT(nb_data->en_bit_idx));
>> +		return NOTIFY_OK;
>> +	default:
>> +		return NOTIFY_DONE;
>> +	};
>> +};
>> +
>>   static struct clk_regmap g12a_vclk2_div = {
>>   	.data = &(struct clk_regmap_div_data){
>>   		.offset = HHI_VIID_CLK_DIV,
>> @@ -3225,10 +3258,18 @@ static struct clk_regmap g12a_vclk2_div = {
>>   			&g12a_vclk2_input.hw
>>   		},
>>   		.num_parents = 1,
>> -		.flags = CLK_GET_RATE_NOCACHE,
>> +		.flags = CLK_DIVIDER_ROUND_CLOSEST,
>>   	},
>>   };
>>   
>> +static struct g12a_vclk_div_notifier g12a_vclk2_div_data = {
>> +	.clk = &g12a_vclk2_div,
>> +	.offset = HHI_VIID_CLK_DIV,
>> +	.en_bit_idx = 16,
>> +	.reset_bit_idx = 17,
>> +	.nb.notifier_call = g12a_vclk_div_notifier_cb,
>> +};
>> +
>>   static struct clk_regmap g12a_vclk = {
>>   	.data = &(struct clk_regmap_gate_data){
>>   		.offset = HHI_VID_CLK_CNTL,
>> @@ -3243,6 +3284,33 @@ static struct clk_regmap g12a_vclk = {
>>   	},
>>   };
>>   
>> +struct g12a_vclk_reset_notifier {
>> +	struct clk_regmap *clk;
>> +	unsigned int offset;
>> +	u8 bit_idx;
>> +	struct notifier_block nb;
>> +};
>> +
>> +static int g12a_vclk_notifier_cb(struct notifier_block *nb,
>> +				  unsigned long event, void *data)
>> +{
>> +	struct g12a_vclk_reset_notifier *nb_data =
>> +		container_of(nb, struct g12a_vclk_reset_notifier, nb);
>> +
>> +	switch (event) {
>> +	case POST_RATE_CHANGE:
>> +		/* reset vclk2 */
>> +		regmap_update_bits(nb_data->clk->map, nb_data->offset,
>> +				   BIT(nb_data->bit_idx), BIT(nb_data->bit_idx));
>> +		regmap_update_bits(nb_data->clk->map, nb_data->offset,
>> +				   BIT(nb_data->bit_idx), 0);
>> +
>> +		return NOTIFY_OK;
>> +	default:
>> +		return NOTIFY_DONE;
>> +	};
>> +}
>> +
>>   static struct clk_regmap g12a_vclk2 = {
>>   	.data = &(struct clk_regmap_gate_data){
>>   		.offset = HHI_VIID_CLK_CNTL,
>> @@ -3253,10 +3321,17 @@ static struct clk_regmap g12a_vclk2 = {
>>   		.ops = &clk_regmap_gate_ops,
>>   		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
>>   		.num_parents = 1,
>> -		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +		.flags = CLK_SET_RATE_PARENT,
>>   	},
>>   };
>>   
>> +static struct g12a_vclk_reset_notifier g12a_vclk2_data = {
>> +	.clk = &g12a_vclk2,
>> +	.offset = HHI_VIID_CLK_CNTL,
>> +	.bit_idx = 15,
>> +	.nb.notifier_call = g12a_vclk_notifier_cb,
>> +};
>> +
>>   static struct clk_regmap g12a_vclk_div1 = {
>>   	.data = &(struct clk_regmap_gate_data){
>>   		.offset = HHI_VID_CLK_CNTL,
>> @@ -3337,7 +3412,7 @@ static struct clk_regmap g12a_vclk2_div1 = {
>>   		.ops = &clk_regmap_gate_ops,
>>   		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>>   		.num_parents = 1,
>> -		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +		.flags = CLK_SET_RATE_PARENT,
>>   	},
>>   };
>>   
>> @@ -3351,7 +3426,7 @@ static struct clk_regmap g12a_vclk2_div2_en = {
>>   		.ops = &clk_regmap_gate_ops,
>>   		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>>   		.num_parents = 1,
>> -		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +		.flags = CLK_SET_RATE_PARENT,
>>   	},
>>   };
>>   
>> @@ -3365,7 +3440,7 @@ static struct clk_regmap g12a_vclk2_div4_en = {
>>   		.ops = &clk_regmap_gate_ops,
>>   		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>>   		.num_parents = 1,
>> -		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +		.flags = CLK_SET_RATE_PARENT,
>>   	},
>>   };
>>   
>> @@ -3379,7 +3454,7 @@ static struct clk_regmap g12a_vclk2_div6_en = {
>>   		.ops = &clk_regmap_gate_ops,
>>   		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>>   		.num_parents = 1,
>> -		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +		.flags = CLK_SET_RATE_PARENT,
>>   	},
>>   };
>>   
>> @@ -3393,7 +3468,7 @@ static struct clk_regmap g12a_vclk2_div12_en = {
>>   		.ops = &clk_regmap_gate_ops,
>>   		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>>   		.num_parents = 1,
>> -		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +		.flags = CLK_SET_RATE_PARENT,
>>   	},
>>   };
>>   
>> @@ -3459,6 +3534,7 @@ static struct clk_fixed_factor g12a_vclk2_div2 = {
>>   			&g12a_vclk2_div2_en.hw
>>   		},
>>   		.num_parents = 1,
>> +		.flags = CLK_SET_RATE_PARENT,
>>   	},
>>   };
>>   
>> @@ -3472,6 +3548,7 @@ static struct clk_fixed_factor g12a_vclk2_div4 = {
>>   			&g12a_vclk2_div4_en.hw
>>   		},
>>   		.num_parents = 1,
>> +		.flags = CLK_SET_RATE_PARENT,
>>   	},
>>   };
>>   
>> @@ -3485,6 +3562,7 @@ static struct clk_fixed_factor g12a_vclk2_div6 = {
>>   			&g12a_vclk2_div6_en.hw
>>   		},
>>   		.num_parents = 1,
>> +		.flags = CLK_SET_RATE_PARENT,
>>   	},
>>   };
>>   
>> @@ -3498,6 +3576,7 @@ static struct clk_fixed_factor g12a_vclk2_div12 = {
>>   			&g12a_vclk2_div12_en.hw
>>   		},
>>   		.num_parents = 1,
>> +		.flags = CLK_SET_RATE_PARENT,
>>   	},
>>   };
>>   
>> @@ -3559,7 +3638,7 @@ static struct clk_regmap g12a_cts_encl_sel = {
>>   		.ops = &clk_regmap_mux_ops,
>>   		.parent_hws = g12a_cts_parent_hws,
>>   		.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
>> -		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
>> +		.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
>>   	},
>>   };
>>   
>> @@ -3727,7 +3806,7 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
>>   	},
>>   	.hw.init = &(struct clk_init_data){
>>   		.name = "mipi_dsi_pxclk_div",
>> -		.ops = &clk_regmap_divider_ops,
>> +		.ops = &clk_regmap_divider_ro_ops,
>>   		.parent_hws = (const struct clk_hw *[]) {
>>   			&g12a_mipi_dsi_pxclk_sel.hw
>>   		},
>> @@ -5421,6 +5500,32 @@ static int meson_g12a_dvfs_setup(struct platform_device *pdev)
>>   	return 0;
>>   }
>>   
>> +static int meson_g12a_vclk_setup(struct platform_device *pdev)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	struct clk *notifier_clk;
>> +	int ret;
>> +
>> +	/* Setup clock notifier for vclk2 */
>> +	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_vclk2.hw, DVFS_CON_ID);
>> +	ret = devm_clk_notifier_register(dev, notifier_clk, &g12a_vclk2_data.nb);
>> +	if (ret) {
>> +		dev_err(dev, "failed to register the vlkc2 notifier\n");
>> +		return ret;
>> +	}
>> +
>> +	/* Setup clock notifier for vclk2_div */
>> +	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_vclk2_div.hw, DVFS_CON_ID);
>> +	ret = devm_clk_notifier_register(dev, notifier_clk,
>> +					 &g12a_vclk2_div_data.nb);
>> +	if (ret) {
>> +		dev_err(dev, "failed to register the vclk2_div notifier\n");
>> +		return ret;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>>   struct meson_g12a_data {
>>   	const struct meson_eeclkc_data eeclkc_data;
>>   	int (*dvfs_setup)(struct platform_device *pdev);
>> @@ -5443,6 +5548,10 @@ static int meson_g12a_probe(struct platform_device *pdev)
>>   	g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
>>   				 eeclkc_data);
>>   
>> +	ret = meson_g12a_vclk_setup(pdev);
>> +	if (ret)
>> +		return ret;
>> +
>>   	if (g12a_data->dvfs_setup)
>>   		return g12a_data->dvfs_setup(pdev);
>

Martin Blumenstingl May 30, 2023, 7:36 p.m. UTC | #5

Hi Neil,

On Tue, May 30, 2023 at 5:57 PM Neil Armstrong
<[e-mail]> wrote:
[...]
> >> The mipi_dsi_pxclk_div is set as RO in order to use the same GP0
> >> for mipi_dsi_pxclk and vclk2_input.
> >
> > I don't think notifiers is the appropriate approach here.
> > Whenever there is clock change the motifiers would trigger an off/on of
> > the clock, regardless of the clock usage or state.
> > If you have several consummers on this vclk2, this would
> > cause glitches and maybe this is not desirable.
> >
> > I think it would be better to handle the enable and reset with a
> > specific gate driver, in prepare() or enable(), and the give the clock
> > CLK_SET_RATE_GATE flag.
> >
> > This would require the clock to be properly turn off before changing the
> > rate.
>
> Sure, will see how to switch to that, seem Martin did than on Meson8.
You can start here: [0]
It may not be the nicest logic but so far it works (for me).

Please note that I don't mix between CCF and direct register IO clock handling:
For the old SoCs I'm relying only on CCF to manage the clocks.


Best regards,
Martin


[0] https://github.com/xdarklight/linux/blob/meson-mx-integration-6.3-20230410/drivers/gpu/drm/meson/meson_vclk.c#L1177-L1179

Jerome Brunet May 31, 2023, 4:08 p.m. UTC | #6

On Tue 30 May 2023 at 17:56, Neil Armstrong <[e-mail]> wrote:

> On 30/05/2023 10:08, Jerome Brunet wrote:
>> On Tue 30 May 2023 at 09:38, Neil Armstrong <[e-mail]>
>> wrote:
>> 
>>> Exposing should not be done in a single commit anymore due to
>>> dt-bindings enforced rules.
>>>
>>> Prepend PRIV to the private CLK IDs so we can add new clock to
>>> the bindings header and in a separate commit remove such private
>>> define and switch to the public CLK IDs identifier.
>>>
>>> This refers to a discussion at [1] with Arnd and Krzysztof.
>>>
>>> [1] https://lore.kernel.org/all/[e-mail]/
>>>
>>> Signed-off-by: Neil Armstrong <[e-mail]>
>> I understand the discussion reported but I don't really like this
>> CLKID_PRIV_
>> It adds another layer of IDs.
>> I'd much prefer if we just expose all the IDs. That would comply with DT
>> new policy and be much simpler in the long run.
>
> While it would solve everything at long term, we'll still need to do the move
> in 3 steps (add PRIV, add to bindings, remove PRIV defined), and we should still

It would certainly be a lot simpler if we could expose the IDs like we used
to one last time to comply with this new requirement.

If it is really not possible, then yes, we will have no choice but to
bounce using this namespace trick. If there is no other choice, then I'd
prefer if it was done for all the IDs of the different SoCs, once and for all.

> decide how to handle NR_CLKS.
>

Can't this stay in the driver header ? This needs to be updated only the
actually adding the clock, isn't it ?

Maybe I'm missing something ...

> Neil
>
>> 
>>> ---
>>>   drivers/clk/meson/g12a.c | 628 +++++++++++++++++++++++------------------------
>>>   drivers/clk/meson/g12a.h | 260 ++++++++++----------
>>>   2 files changed, 444 insertions(+), 444 deletions(-)
>>>
>>> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
>>> index 310accf94830..d2e481ae2429 100644
>>> --- a/drivers/clk/meson/g12a.c
>>> +++ b/drivers/clk/meson/g12a.c
>>> @@ -4255,8 +4255,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
>>>   		[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
>>>   		[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
>>>   		[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
>>> -		[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
>>> -		[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>>> +		[CLKID_PRIV_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
>>> +		[CLKID_PRIV_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>>>   		[CLKID_CLK81]			= &g12a_clk81.hw,
>>>   		[CLKID_MPLL0]			= &g12a_mpll0.hw,
>>>   		[CLKID_MPLL1]			= &g12a_mpll1.hw,
>>> @@ -4307,25 +4307,25 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
>>>   		[CLKID_UART2]			= &g12a_uart2.hw,
>>>   		[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
>>>   		[CLKID_GIC]			= &g12a_gic.hw,
>>> -		[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
>>> -		[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>>> +		[CLKID_PRIV_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
>>> +		[CLKID_PRIV_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>>>   		[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
>>> -		[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
>>> -		[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>>> +		[CLKID_PRIV_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
>>> +		[CLKID_PRIV_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>>>   		[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
>>> -		[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
>>> -		[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>>> +		[CLKID_PRIV_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
>>> +		[CLKID_PRIV_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>>>   		[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
>>> -		[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
>>> -		[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
>>> -		[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
>>> -		[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
>>> -		[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
>>> -		[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
>>> -		[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
>>> -		[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
>>> -		[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
>>> -		[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
>>> +		[CLKID_PRIV_MPLL0_DIV]		= &g12a_mpll0_div.hw,
>>> +		[CLKID_PRIV_MPLL1_DIV]		= &g12a_mpll1_div.hw,
>>> +		[CLKID_PRIV_MPLL2_DIV]		= &g12a_mpll2_div.hw,
>>> +		[CLKID_PRIV_MPLL3_DIV]		= &g12a_mpll3_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV2_DIV]	= &g12a_fclk_div2_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV3_DIV]	= &g12a_fclk_div3_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV4_DIV]	= &g12a_fclk_div4_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV5_DIV]	= &g12a_fclk_div5_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV7_DIV]	= &g12a_fclk_div7_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV2P5_DIV]	= &g12a_fclk_div2p5_div.hw,
>>>   		[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
>>>   		[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
>>>   		[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
>>> @@ -4346,56 +4346,56 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
>>>   		[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
>>>   		[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
>>>   		[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
>>> -		[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
>>> -		[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
>>> -		[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
>>> -		[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
>>> +		[CLKID_PRIV_FIXED_PLL_DCO]	= &g12a_fixed_pll_dco.hw,
>>> +		[CLKID_PRIV_SYS_PLL_DCO]	= &g12a_sys_pll_dco.hw,
>>> +		[CLKID_PRIV_GP0_PLL_DCO]	= &g12a_gp0_pll_dco.hw,
>>> +		[CLKID_PRIV_HIFI_PLL_DCO]	= &g12a_hifi_pll_dco.hw,
>>>   		[CLKID_DMA]			= &g12a_dma.hw,
>>>   		[CLKID_EFUSE]			= &g12a_efuse.hw,
>>>   		[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
>>>   		[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
>>>   		[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
>>> -		[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
>>> +		[CLKID_PRIV_MPLL_PREDIV]	= &g12a_mpll_prediv.hw,
>>>   		[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
>>> -		[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>>> +		[CLKID_PRIV_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>>>   		[CLKID_VPU_0]			= &g12a_vpu_0.hw,
>>>   		[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
>>> -		[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>>> +		[CLKID_PRIV_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>>>   		[CLKID_VPU_1]			= &g12a_vpu_1.hw,
>>>   		[CLKID_VPU]			= &g12a_vpu.hw,
>>>   		[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
>>> -		[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>>> +		[CLKID_PRIV_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>>>   		[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
>>>   		[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
>>> -		[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>>> +		[CLKID_PRIV_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>>>   		[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
>>>   		[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
>>>   		[CLKID_VAPB]			= &g12a_vapb.hw,
>>> -		[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
>>> -		[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
>>> -		[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
>>> +		[CLKID_PRIV_HDMI_PLL_DCO]	= &g12a_hdmi_pll_dco.hw,
>>> +		[CLKID_PRIV_HDMI_PLL_OD]	= &g12a_hdmi_pll_od.hw,
>>> +		[CLKID_PRIV_HDMI_PLL_OD2]	= &g12a_hdmi_pll_od2.hw,
>>>   		[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
>>>   		[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
>>> -		[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
>>> -		[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
>>> -		[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
>>> -		[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
>>> -		[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
>>> -		[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
>>> -		[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
>>> -		[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>>> +		[CLKID_PRIV_VID_PLL_SEL]	= &g12a_vid_pll_sel.hw,
>>> +		[CLKID_PRIV_VID_PLL_DIV]	= &g12a_vid_pll.hw,
>>> +		[CLKID_PRIV_VCLK_SEL]		= &g12a_vclk_sel.hw,
>>> +		[CLKID_PRIV_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
>>> +		[CLKID_PRIV_VCLK_INPUT]		= &g12a_vclk_input.hw,
>>> +		[CLKID_PRIV_VCLK2_INPUT]	= &g12a_vclk2_input.hw,
>>> +		[CLKID_PRIV_VCLK_DIV]		= &g12a_vclk_div.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>>>   		[CLKID_VCLK]			= &g12a_vclk.hw,
>>>   		[CLKID_VCLK2]			= &g12a_vclk2.hw,
>>>   		[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
>>> -		[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
>>> -		[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
>>> -		[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
>>> -		[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
>>> +		[CLKID_PRIV_VCLK_DIV2_EN]	= &g12a_vclk_div2_en.hw,
>>> +		[CLKID_PRIV_VCLK_DIV4_EN]	= &g12a_vclk_div4_en.hw,
>>> +		[CLKID_PRIV_VCLK_DIV6_EN]	= &g12a_vclk_div6_en.hw,
>>> +		[CLKID_PRIV_VCLK_DIV12_EN]	= &g12a_vclk_div12_en.hw,
>>>   		[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
>>> -		[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
>>> -		[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
>>> -		[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
>>> -		[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV2_EN]	= &g12a_vclk2_div2_en.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV4_EN]	= &g12a_vclk2_div4_en.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV6_EN]	= &g12a_vclk2_div6_en.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV12_EN]	= &g12a_vclk2_div12_en.hw,
>>>   		[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
>>>   		[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
>>>   		[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
>>> @@ -4404,69 +4404,69 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
>>>   		[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
>>>   		[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
>>>   		[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
>>> -		[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
>>> -		[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
>>> -		[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
>>> -		[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
>>> +		[CLKID_PRIV_CTS_ENCI_SEL]	= &g12a_cts_enci_sel.hw,
>>> +		[CLKID_PRIV_CTS_ENCP_SEL]	= &g12a_cts_encp_sel.hw,
>>> +		[CLKID_PRIV_CTS_VDAC_SEL]	= &g12a_cts_vdac_sel.hw,
>>> +		[CLKID_PRIV_HDMI_TX_SEL]	= &g12a_hdmi_tx_sel.hw,
>>>   		[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
>>>   		[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
>>>   		[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
>>>   		[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
>>> -		[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
>>> -		[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
>>> +		[CLKID_PRIV_HDMI_SEL]		= &g12a_hdmi_sel.hw,
>>> +		[CLKID_PRIV_HDMI_DIV]		= &g12a_hdmi_div.hw,
>>>   		[CLKID_HDMI]			= &g12a_hdmi.hw,
>>>   		[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
>>> -		[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>>> +		[CLKID_PRIV_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>>>   		[CLKID_MALI_0]			= &g12a_mali_0.hw,
>>>   		[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
>>> -		[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>>> +		[CLKID_PRIV_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>>>   		[CLKID_MALI_1]			= &g12a_mali_1.hw,
>>>   		[CLKID_MALI]			= &g12a_mali.hw,
>>> -		[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
>>> +		[CLKID_PRIV_MPLL_50M_DIV]	= &g12a_mpll_50m_div.hw,
>>>   		[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
>>> -		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
>>> -		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
>>> -		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
>>> -		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
>>> -		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
>>> -		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
>>> -		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
>>> -		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
>>> -		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
>>> +		[CLKID_PRIV_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
>>> +		[CLKID_PRIV_SYS_PLL_DIV16]	= &g12a_sys_pll_div16.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN0]	= &g12a_cpu_clk_postmux0.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN1]	= &g12a_cpu_clk_postmux1.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN]	= &g12a_cpu_clk_dyn.hw,
>>>   		[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,
>>> -		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
>>> -		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
>>> -		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
>>> -		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
>>> -		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
>>> -		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
>>> -		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
>>> -		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
>>> -		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
>>> -		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
>>> -		[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
>>> -		[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
>>> -		[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DIV16]	= &g12a_cpu_clk_div16.hw,
>>> +		[CLKID_PRIV_CPU_CLK_APB_DIV]	= &g12a_cpu_clk_apb_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_APB]	= &g12a_cpu_clk_apb.hw,
>>> +		[CLKID_PRIV_CPU_CLK_ATB_DIV]	= &g12a_cpu_clk_atb_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_ATB]	= &g12a_cpu_clk_atb.hw,
>>> +		[CLKID_PRIV_CPU_CLK_AXI_DIV]	= &g12a_cpu_clk_axi_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_AXI]	= &g12a_cpu_clk_axi.hw,
>>> +		[CLKID_PRIV_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_TRACE]	= &g12a_cpu_clk_trace.hw,
>>> +		[CLKID_PRIV_PCIE_PLL_DCO]	= &g12a_pcie_pll_dco.hw,
>>> +		[CLKID_PRIV_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
>>> +		[CLKID_PRIV_PCIE_PLL_OD]	= &g12a_pcie_pll_od.hw,
>>>   		[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
>>> -		[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
>>> -		[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>>> +		[CLKID_PRIV_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
>>> +		[CLKID_PRIV_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>>>   		[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
>>> -		[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
>>> -		[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
>>> +		[CLKID_PRIV_VDEC_HEVC_SEL]	= &g12a_vdec_hevc_sel.hw,
>>> +		[CLKID_PRIV_VDEC_HEVC_DIV]	= &g12a_vdec_hevc_div.hw,
>>>   		[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
>>> -		[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
>>> -		[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
>>> +		[CLKID_PRIV_VDEC_HEVCF_SEL]	= &g12a_vdec_hevcf_sel.hw,
>>> +		[CLKID_PRIV_VDEC_HEVCF_DIV]	= &g12a_vdec_hevcf_div.hw,
>>>   		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
>>> -		[CLKID_TS_DIV]			= &g12a_ts_div.hw,
>>> +		[CLKID_PRIV_TS_DIV]		= &g12a_ts_div.hw,
>>>   		[CLKID_TS]			= &g12a_ts.hw,
>>> -		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
>>> -		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
>>> +		[CLKID_PRIV_SPICC0_SCLK_SEL]	= &g12a_spicc0_sclk_sel.hw,
>>> +		[CLKID_PRIV_SPICC0_SCLK_DIV]	= &g12a_spicc0_sclk_div.hw,
>>>   		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
>>> -		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
>>> -		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
>>> +		[CLKID_PRIV_SPICC1_SCLK_SEL]	= &g12a_spicc1_sclk_sel.hw,
>>> +		[CLKID_PRIV_SPICC1_SCLK_DIV]	= &g12a_spicc1_sclk_div.hw,
>>>   		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
>>>   		[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
>>> -		[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>>> +		[CLKID_PRIV_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>>>   		[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
>>>   		[NR_CLKS]			= NULL,
>>>   	},
>>> @@ -4484,8 +4484,8 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
>>>   		[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
>>>   		[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
>>>   		[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
>>> -		[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
>>> -		[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>>> +		[CLKID_PRIV_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
>>> +		[CLKID_PRIV_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>>>   		[CLKID_CLK81]			= &g12a_clk81.hw,
>>>   		[CLKID_MPLL0]			= &g12a_mpll0.hw,
>>>   		[CLKID_MPLL1]			= &g12a_mpll1.hw,
>>> @@ -4536,25 +4536,25 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
>>>   		[CLKID_UART2]			= &g12a_uart2.hw,
>>>   		[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
>>>   		[CLKID_GIC]			= &g12a_gic.hw,
>>> -		[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
>>> -		[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>>> +		[CLKID_PRIV_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
>>> +		[CLKID_PRIV_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>>>   		[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
>>> -		[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
>>> -		[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>>> +		[CLKID_PRIV_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
>>> +		[CLKID_PRIV_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>>>   		[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
>>> -		[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
>>> -		[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>>> +		[CLKID_PRIV_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
>>> +		[CLKID_PRIV_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>>>   		[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
>>> -		[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
>>> -		[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
>>> -		[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
>>> -		[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
>>> -		[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
>>> -		[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
>>> -		[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
>>> -		[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
>>> -		[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
>>> -		[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
>>> +		[CLKID_PRIV_MPLL0_DIV]		= &g12a_mpll0_div.hw,
>>> +		[CLKID_PRIV_MPLL1_DIV]		= &g12a_mpll1_div.hw,
>>> +		[CLKID_PRIV_MPLL2_DIV]		= &g12a_mpll2_div.hw,
>>> +		[CLKID_PRIV_MPLL3_DIV]		= &g12a_mpll3_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV2_DIV]	= &g12a_fclk_div2_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV3_DIV]	= &g12a_fclk_div3_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV4_DIV]	= &g12a_fclk_div4_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV5_DIV]	= &g12a_fclk_div5_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV7_DIV]	= &g12a_fclk_div7_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV2P5_DIV]	= &g12a_fclk_div2p5_div.hw,
>>>   		[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
>>>   		[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
>>>   		[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
>>> @@ -4575,56 +4575,56 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
>>>   		[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
>>>   		[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
>>>   		[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
>>> -		[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
>>> -		[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
>>> -		[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
>>> -		[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
>>> +		[CLKID_PRIV_FIXED_PLL_DCO]	= &g12a_fixed_pll_dco.hw,
>>> +		[CLKID_PRIV_SYS_PLL_DCO]	= &g12a_sys_pll_dco.hw,
>>> +		[CLKID_PRIV_GP0_PLL_DCO]	= &g12a_gp0_pll_dco.hw,
>>> +		[CLKID_PRIV_HIFI_PLL_DCO]	= &g12a_hifi_pll_dco.hw,
>>>   		[CLKID_DMA]			= &g12a_dma.hw,
>>>   		[CLKID_EFUSE]			= &g12a_efuse.hw,
>>>   		[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
>>>   		[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
>>>   		[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
>>> -		[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
>>> +		[CLKID_PRIV_MPLL_PREDIV]	= &g12a_mpll_prediv.hw,
>>>   		[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
>>> -		[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>>> +		[CLKID_PRIV_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>>>   		[CLKID_VPU_0]			= &g12a_vpu_0.hw,
>>>   		[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
>>> -		[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>>> +		[CLKID_PRIV_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>>>   		[CLKID_VPU_1]			= &g12a_vpu_1.hw,
>>>   		[CLKID_VPU]			= &g12a_vpu.hw,
>>>   		[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
>>> -		[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>>> +		[CLKID_PRIV_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>>>   		[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
>>>   		[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
>>> -		[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>>> +		[CLKID_PRIV_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>>>   		[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
>>>   		[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
>>>   		[CLKID_VAPB]			= &g12a_vapb.hw,
>>> -		[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
>>> -		[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
>>> -		[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
>>> +		[CLKID_PRIV_HDMI_PLL_DCO]	= &g12a_hdmi_pll_dco.hw,
>>> +		[CLKID_PRIV_HDMI_PLL_OD]	= &g12a_hdmi_pll_od.hw,
>>> +		[CLKID_PRIV_HDMI_PLL_OD2]	= &g12a_hdmi_pll_od2.hw,
>>>   		[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
>>>   		[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
>>> -		[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
>>> -		[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
>>> -		[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
>>> -		[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
>>> -		[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
>>> -		[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
>>> -		[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
>>> -		[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>>> +		[CLKID_PRIV_VID_PLL_SEL]	= &g12a_vid_pll_sel.hw,
>>> +		[CLKID_PRIV_VID_PLL_DIV]	= &g12a_vid_pll.hw,
>>> +		[CLKID_PRIV_VCLK_SEL]		= &g12a_vclk_sel.hw,
>>> +		[CLKID_PRIV_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
>>> +		[CLKID_PRIV_VCLK_INPUT]		= &g12a_vclk_input.hw,
>>> +		[CLKID_PRIV_VCLK2_INPUT]	= &g12a_vclk2_input.hw,
>>> +		[CLKID_PRIV_VCLK_DIV]		= &g12a_vclk_div.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>>>   		[CLKID_VCLK]			= &g12a_vclk.hw,
>>>   		[CLKID_VCLK2]			= &g12a_vclk2.hw,
>>>   		[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
>>> -		[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
>>> -		[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
>>> -		[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
>>> -		[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
>>> +		[CLKID_PRIV_VCLK_DIV2_EN]	= &g12a_vclk_div2_en.hw,
>>> +		[CLKID_PRIV_VCLK_DIV4_EN]	= &g12a_vclk_div4_en.hw,
>>> +		[CLKID_PRIV_VCLK_DIV6_EN]	= &g12a_vclk_div6_en.hw,
>>> +		[CLKID_PRIV_VCLK_DIV12_EN]	= &g12a_vclk_div12_en.hw,
>>>   		[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
>>> -		[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
>>> -		[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
>>> -		[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
>>> -		[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV2_EN]	= &g12a_vclk2_div2_en.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV4_EN]	= &g12a_vclk2_div4_en.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV6_EN]	= &g12a_vclk2_div6_en.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV12_EN]	= &g12a_vclk2_div12_en.hw,
>>>   		[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
>>>   		[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
>>>   		[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
>>> @@ -4633,104 +4633,104 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
>>>   		[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
>>>   		[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
>>>   		[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
>>> -		[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
>>> -		[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
>>> -		[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
>>> -		[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
>>> +		[CLKID_PRIV_CTS_ENCI_SEL]	= &g12a_cts_enci_sel.hw,
>>> +		[CLKID_PRIV_CTS_ENCP_SEL]	= &g12a_cts_encp_sel.hw,
>>> +		[CLKID_PRIV_CTS_VDAC_SEL]	= &g12a_cts_vdac_sel.hw,
>>> +		[CLKID_PRIV_HDMI_TX_SEL]	= &g12a_hdmi_tx_sel.hw,
>>>   		[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
>>>   		[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
>>>   		[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
>>>   		[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
>>> -		[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
>>> -		[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
>>> +		[CLKID_PRIV_HDMI_SEL]		= &g12a_hdmi_sel.hw,
>>> +		[CLKID_PRIV_HDMI_DIV]		= &g12a_hdmi_div.hw,
>>>   		[CLKID_HDMI]			= &g12a_hdmi.hw,
>>>   		[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
>>> -		[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>>> +		[CLKID_PRIV_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>>>   		[CLKID_MALI_0]			= &g12a_mali_0.hw,
>>>   		[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
>>> -		[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>>> +		[CLKID_PRIV_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>>>   		[CLKID_MALI_1]			= &g12a_mali_1.hw,
>>>   		[CLKID_MALI]			= &g12a_mali.hw,
>>> -		[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
>>> +		[CLKID_PRIV_MPLL_50M_DIV]	= &g12a_mpll_50m_div.hw,
>>>   		[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
>>> -		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
>>> -		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
>>> -		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
>>> -		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
>>> -		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
>>> -		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
>>> -		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
>>> -		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
>>> -		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
>>> +		[CLKID_PRIV_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
>>> +		[CLKID_PRIV_SYS_PLL_DIV16]	= &g12a_sys_pll_div16.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN0]	= &g12a_cpu_clk_postmux0.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN1]	= &g12a_cpu_clk_postmux1.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN]	= &g12a_cpu_clk_dyn.hw,
>>>   		[CLKID_CPU_CLK]			= &g12b_cpu_clk.hw,
>>> -		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
>>> -		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
>>> -		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
>>> -		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
>>> -		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
>>> -		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
>>> -		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
>>> -		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
>>> -		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
>>> -		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
>>> -		[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
>>> -		[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
>>> -		[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DIV16]	= &g12a_cpu_clk_div16.hw,
>>> +		[CLKID_PRIV_CPU_CLK_APB_DIV]	= &g12a_cpu_clk_apb_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_APB]	= &g12a_cpu_clk_apb.hw,
>>> +		[CLKID_PRIV_CPU_CLK_ATB_DIV]	= &g12a_cpu_clk_atb_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_ATB]	= &g12a_cpu_clk_atb.hw,
>>> +		[CLKID_PRIV_CPU_CLK_AXI_DIV]	= &g12a_cpu_clk_axi_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_AXI]	= &g12a_cpu_clk_axi.hw,
>>> +		[CLKID_PRIV_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_TRACE]	= &g12a_cpu_clk_trace.hw,
>>> +		[CLKID_PRIV_PCIE_PLL_DCO]	= &g12a_pcie_pll_dco.hw,
>>> +		[CLKID_PRIV_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
>>> +		[CLKID_PRIV_PCIE_PLL_OD]	= &g12a_pcie_pll_od.hw,
>>>   		[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
>>> -		[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
>>> -		[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>>> +		[CLKID_PRIV_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
>>> +		[CLKID_PRIV_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>>>   		[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
>>> -		[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
>>> -		[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
>>> +		[CLKID_PRIV_VDEC_HEVC_SEL]	= &g12a_vdec_hevc_sel.hw,
>>> +		[CLKID_PRIV_VDEC_HEVC_DIV]	= &g12a_vdec_hevc_div.hw,
>>>   		[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
>>> -		[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
>>> -		[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
>>> +		[CLKID_PRIV_VDEC_HEVCF_SEL]	= &g12a_vdec_hevcf_sel.hw,
>>> +		[CLKID_PRIV_VDEC_HEVCF_DIV]	= &g12a_vdec_hevcf_div.hw,
>>>   		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
>>> -		[CLKID_TS_DIV]			= &g12a_ts_div.hw,
>>> +		[CLKID_PRIV_TS_DIV]		= &g12a_ts_div.hw,
>>>   		[CLKID_TS]			= &g12a_ts.hw,
>>> -		[CLKID_SYS1_PLL_DCO]		= &g12b_sys1_pll_dco.hw,
>>> -		[CLKID_SYS1_PLL]		= &g12b_sys1_pll.hw,
>>> -		[CLKID_SYS1_PLL_DIV16_EN]	= &g12b_sys1_pll_div16_en.hw,
>>> -		[CLKID_SYS1_PLL_DIV16]		= &g12b_sys1_pll_div16.hw,
>>> -		[CLKID_CPUB_CLK_DYN0_SEL]	= &g12b_cpub_clk_premux0.hw,
>>> -		[CLKID_CPUB_CLK_DYN0_DIV]	= &g12b_cpub_clk_mux0_div.hw,
>>> -		[CLKID_CPUB_CLK_DYN0]		= &g12b_cpub_clk_postmux0.hw,
>>> -		[CLKID_CPUB_CLK_DYN1_SEL]	= &g12b_cpub_clk_premux1.hw,
>>> -		[CLKID_CPUB_CLK_DYN1_DIV]	= &g12b_cpub_clk_mux1_div.hw,
>>> -		[CLKID_CPUB_CLK_DYN1]		= &g12b_cpub_clk_postmux1.hw,
>>> -		[CLKID_CPUB_CLK_DYN]		= &g12b_cpub_clk_dyn.hw,
>>> +		[CLKID_PRIV_SYS1_PLL_DCO]	= &g12b_sys1_pll_dco.hw,
>>> +		[CLKID_PRIV_SYS1_PLL]		= &g12b_sys1_pll.hw,
>>> +		[CLKID_PRIV_SYS1_PLL_DIV16_EN]	= &g12b_sys1_pll_div16_en.hw,
>>> +		[CLKID_PRIV_SYS1_PLL_DIV16]	= &g12b_sys1_pll_div16.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DYN0_SEL]	= &g12b_cpub_clk_premux0.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DYN0_DIV]	= &g12b_cpub_clk_mux0_div.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DYN0]	= &g12b_cpub_clk_postmux0.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DYN1_SEL]	= &g12b_cpub_clk_premux1.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DYN1_DIV]	= &g12b_cpub_clk_mux1_div.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DYN1]	= &g12b_cpub_clk_postmux1.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DYN]	= &g12b_cpub_clk_dyn.hw,
>>>   		[CLKID_CPUB_CLK]		= &g12b_cpub_clk.hw,
>>> -		[CLKID_CPUB_CLK_DIV16_EN]	= &g12b_cpub_clk_div16_en.hw,
>>> -		[CLKID_CPUB_CLK_DIV16]		= &g12b_cpub_clk_div16.hw,
>>> -		[CLKID_CPUB_CLK_DIV2]		= &g12b_cpub_clk_div2.hw,
>>> -		[CLKID_CPUB_CLK_DIV3]		= &g12b_cpub_clk_div3.hw,
>>> -		[CLKID_CPUB_CLK_DIV4]		= &g12b_cpub_clk_div4.hw,
>>> -		[CLKID_CPUB_CLK_DIV5]		= &g12b_cpub_clk_div5.hw,
>>> -		[CLKID_CPUB_CLK_DIV6]		= &g12b_cpub_clk_div6.hw,
>>> -		[CLKID_CPUB_CLK_DIV7]		= &g12b_cpub_clk_div7.hw,
>>> -		[CLKID_CPUB_CLK_DIV8]		= &g12b_cpub_clk_div8.hw,
>>> -		[CLKID_CPUB_CLK_APB_SEL]	= &g12b_cpub_clk_apb_sel.hw,
>>> -		[CLKID_CPUB_CLK_APB]		= &g12b_cpub_clk_apb.hw,
>>> -		[CLKID_CPUB_CLK_ATB_SEL]	= &g12b_cpub_clk_atb_sel.hw,
>>> -		[CLKID_CPUB_CLK_ATB]		= &g12b_cpub_clk_atb.hw,
>>> -		[CLKID_CPUB_CLK_AXI_SEL]	= &g12b_cpub_clk_axi_sel.hw,
>>> -		[CLKID_CPUB_CLK_AXI]		= &g12b_cpub_clk_axi.hw,
>>> -		[CLKID_CPUB_CLK_TRACE_SEL]	= &g12b_cpub_clk_trace_sel.hw,
>>> -		[CLKID_CPUB_CLK_TRACE]		= &g12b_cpub_clk_trace.hw,
>>> -		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
>>> -		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DIV16_EN]	= &g12b_cpub_clk_div16_en.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DIV16]	= &g12b_cpub_clk_div16.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DIV2]	= &g12b_cpub_clk_div2.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DIV3]	= &g12b_cpub_clk_div3.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DIV4]	= &g12b_cpub_clk_div4.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DIV5]	= &g12b_cpub_clk_div5.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DIV6]	= &g12b_cpub_clk_div6.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DIV7]	= &g12b_cpub_clk_div7.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_DIV8]	= &g12b_cpub_clk_div8.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_APB_SEL]	= &g12b_cpub_clk_apb_sel.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_APB]	= &g12b_cpub_clk_apb.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_ATB_SEL]	= &g12b_cpub_clk_atb_sel.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_ATB]	= &g12b_cpub_clk_atb.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_AXI_SEL]	= &g12b_cpub_clk_axi_sel.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_AXI]	= &g12b_cpub_clk_axi.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_TRACE_SEL]	= &g12b_cpub_clk_trace_sel.hw,
>>> +		[CLKID_PRIV_CPUB_CLK_TRACE]	= &g12b_cpub_clk_trace.hw,
>>> +		[CLKID_PRIV_SPICC0_SCLK_SEL]	= &g12a_spicc0_sclk_sel.hw,
>>> +		[CLKID_PRIV_SPICC0_SCLK_DIV]	= &g12a_spicc0_sclk_div.hw,
>>>   		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
>>> -		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
>>> -		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
>>> +		[CLKID_PRIV_SPICC1_SCLK_SEL]	= &g12a_spicc1_sclk_sel.hw,
>>> +		[CLKID_PRIV_SPICC1_SCLK_DIV]	= &g12a_spicc1_sclk_div.hw,
>>>   		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
>>> -		[CLKID_NNA_AXI_CLK_SEL]		= &sm1_nna_axi_clk_sel.hw,
>>> -		[CLKID_NNA_AXI_CLK_DIV]		= &sm1_nna_axi_clk_div.hw,
>>> +		[CLKID_PRIV_NNA_AXI_CLK_SEL]	= &sm1_nna_axi_clk_sel.hw,
>>> +		[CLKID_PRIV_NNA_AXI_CLK_DIV]	= &sm1_nna_axi_clk_div.hw,
>>>   		[CLKID_NNA_AXI_CLK]		= &sm1_nna_axi_clk.hw,
>>> -		[CLKID_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
>>> -		[CLKID_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
>>> +		[CLKID_PRIV_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
>>> +		[CLKID_PRIV_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
>>>   		[CLKID_NNA_CORE_CLK]		= &sm1_nna_core_clk.hw,
>>>   		[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
>>> -		[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>>> +		[CLKID_PRIV_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>>>   		[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
>>>   		[NR_CLKS]			= NULL,
>>>   	},
>>> @@ -4748,8 +4748,8 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
>>>   		[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
>>>   		[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
>>>   		[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
>>> -		[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
>>> -		[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>>> +		[CLKID_PRIV_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
>>> +		[CLKID_PRIV_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
>>>   		[CLKID_CLK81]			= &g12a_clk81.hw,
>>>   		[CLKID_MPLL0]			= &g12a_mpll0.hw,
>>>   		[CLKID_MPLL1]			= &g12a_mpll1.hw,
>>> @@ -4800,25 +4800,25 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
>>>   		[CLKID_UART2]			= &g12a_uart2.hw,
>>>   		[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
>>>   		[CLKID_GIC]			= &g12a_gic.hw,
>>> -		[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
>>> -		[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>>> +		[CLKID_PRIV_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
>>> +		[CLKID_PRIV_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
>>>   		[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
>>> -		[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
>>> -		[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>>> +		[CLKID_PRIV_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
>>> +		[CLKID_PRIV_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
>>>   		[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
>>> -		[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
>>> -		[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>>> +		[CLKID_PRIV_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
>>> +		[CLKID_PRIV_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
>>>   		[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
>>> -		[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
>>> -		[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
>>> -		[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
>>> -		[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
>>> -		[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
>>> -		[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
>>> -		[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
>>> -		[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
>>> -		[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
>>> -		[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
>>> +		[CLKID_PRIV_MPLL0_DIV]		= &g12a_mpll0_div.hw,
>>> +		[CLKID_PRIV_MPLL1_DIV]		= &g12a_mpll1_div.hw,
>>> +		[CLKID_PRIV_MPLL2_DIV]		= &g12a_mpll2_div.hw,
>>> +		[CLKID_PRIV_MPLL3_DIV]		= &g12a_mpll3_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV2_DIV]	= &g12a_fclk_div2_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV3_DIV]	= &g12a_fclk_div3_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV4_DIV]	= &g12a_fclk_div4_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV5_DIV]	= &g12a_fclk_div5_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV7_DIV]	= &g12a_fclk_div7_div.hw,
>>> +		[CLKID_PRIV_FCLK_DIV2P5_DIV]	= &g12a_fclk_div2p5_div.hw,
>>>   		[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
>>>   		[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
>>>   		[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
>>> @@ -4839,56 +4839,56 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
>>>   		[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
>>>   		[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
>>>   		[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
>>> -		[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
>>> -		[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
>>> -		[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
>>> -		[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
>>> +		[CLKID_PRIV_FIXED_PLL_DCO]	= &g12a_fixed_pll_dco.hw,
>>> +		[CLKID_PRIV_SYS_PLL_DCO]	= &g12a_sys_pll_dco.hw,
>>> +		[CLKID_PRIV_GP0_PLL_DCO]	= &g12a_gp0_pll_dco.hw,
>>> +		[CLKID_PRIV_HIFI_PLL_DCO]	= &g12a_hifi_pll_dco.hw,
>>>   		[CLKID_DMA]			= &g12a_dma.hw,
>>>   		[CLKID_EFUSE]			= &g12a_efuse.hw,
>>>   		[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
>>>   		[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
>>>   		[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
>>> -		[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
>>> +		[CLKID_PRIV_MPLL_PREDIV]	= &g12a_mpll_prediv.hw,
>>>   		[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
>>> -		[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>>> +		[CLKID_PRIV_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
>>>   		[CLKID_VPU_0]			= &g12a_vpu_0.hw,
>>>   		[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
>>> -		[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>>> +		[CLKID_PRIV_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
>>>   		[CLKID_VPU_1]			= &g12a_vpu_1.hw,
>>>   		[CLKID_VPU]			= &g12a_vpu.hw,
>>>   		[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
>>> -		[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>>> +		[CLKID_PRIV_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
>>>   		[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
>>>   		[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
>>> -		[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>>> +		[CLKID_PRIV_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
>>>   		[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
>>>   		[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
>>>   		[CLKID_VAPB]			= &g12a_vapb.hw,
>>> -		[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
>>> -		[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
>>> -		[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
>>> +		[CLKID_PRIV_HDMI_PLL_DCO]	= &g12a_hdmi_pll_dco.hw,
>>> +		[CLKID_PRIV_HDMI_PLL_OD]	= &g12a_hdmi_pll_od.hw,
>>> +		[CLKID_PRIV_HDMI_PLL_OD2]	= &g12a_hdmi_pll_od2.hw,
>>>   		[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
>>>   		[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
>>> -		[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
>>> -		[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
>>> -		[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
>>> -		[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
>>> -		[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
>>> -		[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
>>> -		[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
>>> -		[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>>> +		[CLKID_PRIV_VID_PLL_SEL]	= &g12a_vid_pll_sel.hw,
>>> +		[CLKID_PRIV_VID_PLL_DIV]	= &g12a_vid_pll.hw,
>>> +		[CLKID_PRIV_VCLK_SEL]		= &g12a_vclk_sel.hw,
>>> +		[CLKID_PRIV_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
>>> +		[CLKID_PRIV_VCLK_INPUT]		= &g12a_vclk_input.hw,
>>> +		[CLKID_PRIV_VCLK2_INPUT]	= &g12a_vclk2_input.hw,
>>> +		[CLKID_PRIV_VCLK_DIV]		= &g12a_vclk_div.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV]		= &g12a_vclk2_div.hw,
>>>   		[CLKID_VCLK]			= &g12a_vclk.hw,
>>>   		[CLKID_VCLK2]			= &g12a_vclk2.hw,
>>>   		[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
>>> -		[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
>>> -		[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
>>> -		[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
>>> -		[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
>>> +		[CLKID_PRIV_VCLK_DIV2_EN]	= &g12a_vclk_div2_en.hw,
>>> +		[CLKID_PRIV_VCLK_DIV4_EN]	= &g12a_vclk_div4_en.hw,
>>> +		[CLKID_PRIV_VCLK_DIV6_EN]	= &g12a_vclk_div6_en.hw,
>>> +		[CLKID_PRIV_VCLK_DIV12_EN]	= &g12a_vclk_div12_en.hw,
>>>   		[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
>>> -		[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
>>> -		[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
>>> -		[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
>>> -		[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV2_EN]	= &g12a_vclk2_div2_en.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV4_EN]	= &g12a_vclk2_div4_en.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV6_EN]	= &g12a_vclk2_div6_en.hw,
>>> +		[CLKID_PRIV_VCLK2_DIV12_EN]	= &g12a_vclk2_div12_en.hw,
>>>   		[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
>>>   		[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
>>>   		[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
>>> @@ -4897,89 +4897,89 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
>>>   		[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
>>>   		[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
>>>   		[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
>>> -		[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
>>> -		[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
>>> -		[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
>>> -		[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
>>> +		[CLKID_PRIV_CTS_ENCI_SEL]	= &g12a_cts_enci_sel.hw,
>>> +		[CLKID_PRIV_CTS_ENCP_SEL]	= &g12a_cts_encp_sel.hw,
>>> +		[CLKID_PRIV_CTS_VDAC_SEL]	= &g12a_cts_vdac_sel.hw,
>>> +		[CLKID_PRIV_HDMI_TX_SEL]	= &g12a_hdmi_tx_sel.hw,
>>>   		[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
>>>   		[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
>>>   		[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
>>>   		[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
>>> -		[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
>>> -		[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
>>> +		[CLKID_PRIV_HDMI_SEL]		= &g12a_hdmi_sel.hw,
>>> +		[CLKID_PRIV_HDMI_DIV]		= &g12a_hdmi_div.hw,
>>>   		[CLKID_HDMI]			= &g12a_hdmi.hw,
>>>   		[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
>>> -		[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>>> +		[CLKID_PRIV_MALI_0_DIV]		= &g12a_mali_0_div.hw,
>>>   		[CLKID_MALI_0]			= &g12a_mali_0.hw,
>>>   		[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
>>> -		[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>>> +		[CLKID_PRIV_MALI_1_DIV]		= &g12a_mali_1_div.hw,
>>>   		[CLKID_MALI_1]			= &g12a_mali_1.hw,
>>>   		[CLKID_MALI]			= &g12a_mali.hw,
>>> -		[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
>>> +		[CLKID_PRIV_MPLL_50M_DIV]	= &g12a_mpll_50m_div.hw,
>>>   		[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
>>> -		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
>>> -		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
>>> -		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
>>> -		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
>>> -		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
>>> -		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
>>> -		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
>>> -		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
>>> -		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
>>> +		[CLKID_PRIV_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
>>> +		[CLKID_PRIV_SYS_PLL_DIV16]	= &g12a_sys_pll_div16.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN0]	= &g12a_cpu_clk_postmux0.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN1]	= &g12a_cpu_clk_postmux1.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DYN]	= &g12a_cpu_clk_dyn.hw,
>>>   		[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,
>>> -		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
>>> -		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
>>> -		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
>>> -		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
>>> -		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
>>> -		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
>>> -		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
>>> -		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
>>> -		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
>>> -		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
>>> -		[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
>>> -		[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
>>> -		[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
>>> +		[CLKID_PRIV_CPU_CLK_DIV16]	= &g12a_cpu_clk_div16.hw,
>>> +		[CLKID_PRIV_CPU_CLK_APB_DIV]	= &g12a_cpu_clk_apb_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_APB]	= &g12a_cpu_clk_apb.hw,
>>> +		[CLKID_PRIV_CPU_CLK_ATB_DIV]	= &g12a_cpu_clk_atb_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_ATB]	= &g12a_cpu_clk_atb.hw,
>>> +		[CLKID_PRIV_CPU_CLK_AXI_DIV]	= &g12a_cpu_clk_axi_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_AXI]	= &g12a_cpu_clk_axi.hw,
>>> +		[CLKID_PRIV_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
>>> +		[CLKID_PRIV_CPU_CLK_TRACE]	= &g12a_cpu_clk_trace.hw,
>>> +		[CLKID_PRIV_PCIE_PLL_DCO]	= &g12a_pcie_pll_dco.hw,
>>> +		[CLKID_PRIV_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
>>> +		[CLKID_PRIV_PCIE_PLL_OD]	= &g12a_pcie_pll_od.hw,
>>>   		[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
>>> -		[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
>>> -		[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>>> +		[CLKID_PRIV_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
>>> +		[CLKID_PRIV_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
>>>   		[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
>>> -		[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
>>> -		[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
>>> +		[CLKID_PRIV_VDEC_HEVC_SEL]	= &g12a_vdec_hevc_sel.hw,
>>> +		[CLKID_PRIV_VDEC_HEVC_DIV]	= &g12a_vdec_hevc_div.hw,
>>>   		[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
>>> -		[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
>>> -		[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
>>> +		[CLKID_PRIV_VDEC_HEVCF_SEL]	= &g12a_vdec_hevcf_sel.hw,
>>> +		[CLKID_PRIV_VDEC_HEVCF_DIV]	= &g12a_vdec_hevcf_div.hw,
>>>   		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
>>> -		[CLKID_TS_DIV]			= &g12a_ts_div.hw,
>>> +		[CLKID_PRIV_TS_DIV]		= &g12a_ts_div.hw,
>>>   		[CLKID_TS]			= &g12a_ts.hw,
>>> -		[CLKID_GP1_PLL_DCO]		= &sm1_gp1_pll_dco.hw,
>>> +		[CLKID_PRIV_GP1_PLL_DCO]	= &sm1_gp1_pll_dco.hw,
>>>   		[CLKID_GP1_PLL]			= &sm1_gp1_pll.hw,
>>> -		[CLKID_DSU_CLK_DYN0_SEL]	= &sm1_dsu_clk_premux0.hw,
>>> -		[CLKID_DSU_CLK_DYN0_DIV]	= &sm1_dsu_clk_premux1.hw,
>>> -		[CLKID_DSU_CLK_DYN0]		= &sm1_dsu_clk_mux0_div.hw,
>>> -		[CLKID_DSU_CLK_DYN1_SEL]	= &sm1_dsu_clk_postmux0.hw,
>>> -		[CLKID_DSU_CLK_DYN1_DIV]	= &sm1_dsu_clk_mux1_div.hw,
>>> -		[CLKID_DSU_CLK_DYN1]		= &sm1_dsu_clk_postmux1.hw,
>>> -		[CLKID_DSU_CLK_DYN]		= &sm1_dsu_clk_dyn.hw,
>>> -		[CLKID_DSU_CLK_FINAL]		= &sm1_dsu_final_clk.hw,
>>> +		[CLKID_PRIV_DSU_CLK_DYN0_SEL]	= &sm1_dsu_clk_premux0.hw,
>>> +		[CLKID_PRIV_DSU_CLK_DYN0_DIV]	= &sm1_dsu_clk_premux1.hw,
>>> +		[CLKID_PRIV_DSU_CLK_DYN0]	= &sm1_dsu_clk_mux0_div.hw,
>>> +		[CLKID_PRIV_DSU_CLK_DYN1_SEL]	= &sm1_dsu_clk_postmux0.hw,
>>> +		[CLKID_PRIV_DSU_CLK_DYN1_DIV]	= &sm1_dsu_clk_mux1_div.hw,
>>> +		[CLKID_PRIV_DSU_CLK_DYN1]	= &sm1_dsu_clk_postmux1.hw,
>>> +		[CLKID_PRIV_DSU_CLK_DYN]	= &sm1_dsu_clk_dyn.hw,
>>> +		[CLKID_PRIV_DSU_CLK_FINAL]	= &sm1_dsu_final_clk.hw,
>>>   		[CLKID_DSU_CLK]			= &sm1_dsu_clk.hw,
>>>   		[CLKID_CPU1_CLK]		= &sm1_cpu1_clk.hw,
>>>   		[CLKID_CPU2_CLK]		= &sm1_cpu2_clk.hw,
>>>   		[CLKID_CPU3_CLK]		= &sm1_cpu3_clk.hw,
>>> -		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
>>> -		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
>>> +		[CLKID_PRIV_SPICC0_SCLK_SEL]	= &g12a_spicc0_sclk_sel.hw,
>>> +		[CLKID_PRIV_SPICC0_SCLK_DIV]	= &g12a_spicc0_sclk_div.hw,
>>>   		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
>>> -		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
>>> -		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
>>> +		[CLKID_PRIV_SPICC1_SCLK_SEL]	= &g12a_spicc1_sclk_sel.hw,
>>> +		[CLKID_PRIV_SPICC1_SCLK_DIV]	= &g12a_spicc1_sclk_div.hw,
>>>   		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
>>> -		[CLKID_NNA_AXI_CLK_SEL]		= &sm1_nna_axi_clk_sel.hw,
>>> -		[CLKID_NNA_AXI_CLK_DIV]		= &sm1_nna_axi_clk_div.hw,
>>> +		[CLKID_PRIV_NNA_AXI_CLK_SEL]	= &sm1_nna_axi_clk_sel.hw,
>>> +		[CLKID_PRIV_NNA_AXI_CLK_DIV]	= &sm1_nna_axi_clk_div.hw,
>>>   		[CLKID_NNA_AXI_CLK]		= &sm1_nna_axi_clk.hw,
>>> -		[CLKID_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
>>> -		[CLKID_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
>>> +		[CLKID_PRIV_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
>>> +		[CLKID_PRIV_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
>>>   		[CLKID_NNA_CORE_CLK]		= &sm1_nna_core_clk.hw,
>>>   		[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
>>> -		[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>>> +		[CLKID_PRIV_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
>>>   		[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
>>>   		[NR_CLKS]			= NULL,
>>>   	},
>>> @@ -5246,7 +5246,7 @@ static int meson_g12a_dvfs_setup_common(struct device *dev,
>>>   	struct clk_hw *xtal;
>>>   	int ret;
>>>   -	xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
>>> +	xtal = clk_hw_get_parent_by_index(hws[CLKID_PRIV_CPU_CLK_DYN1_SEL], 0);
>>>     	/* Setup clock notifier for cpu_clk_postmux0 */
>>>   	g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
>>> @@ -5284,7 +5284,7 @@ static int meson_g12b_dvfs_setup(struct platform_device *pdev)
>>>   	if (ret)
>>>   		return ret;
>>>   -	xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
>>> +	xtal = clk_hw_get_parent_by_index(hws[CLKID_PRIV_CPU_CLK_DYN1_SEL], 0);
>>>     	/* Setup clock notifier for cpu_clk mux */
>>>   	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw,
>>> diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
>>> index a97613df38b3..a57f4a9717db 100644
>>> --- a/drivers/clk/meson/g12a.h
>>> +++ b/drivers/clk/meson/g12a.h
>>> @@ -135,136 +135,136 @@
>>>    * to expose, such as the internal muxes and dividers of composite clocks,
>>>    * will remain defined here.
>>>    */
>>> -#define CLKID_MPEG_SEL				8
>>> -#define CLKID_MPEG_DIV				9
>>> -#define CLKID_SD_EMMC_A_CLK0_SEL		63
>>> -#define CLKID_SD_EMMC_A_CLK0_DIV		64
>>> -#define CLKID_SD_EMMC_B_CLK0_SEL		65
>>> -#define CLKID_SD_EMMC_B_CLK0_DIV		66
>>> -#define CLKID_SD_EMMC_C_CLK0_SEL		67
>>> -#define CLKID_SD_EMMC_C_CLK0_DIV		68
>>> -#define CLKID_MPLL0_DIV				69
>>> -#define CLKID_MPLL1_DIV				70
>>> -#define CLKID_MPLL2_DIV				71
>>> -#define CLKID_MPLL3_DIV				72
>>> -#define CLKID_MPLL_PREDIV			73
>>> -#define CLKID_FCLK_DIV2_DIV			75
>>> -#define CLKID_FCLK_DIV3_DIV			76
>>> -#define CLKID_FCLK_DIV4_DIV			77
>>> -#define CLKID_FCLK_DIV5_DIV			78
>>> -#define CLKID_FCLK_DIV7_DIV			79
>>> -#define CLKID_FCLK_DIV2P5_DIV			100
>>> -#define CLKID_FIXED_PLL_DCO			101
>>> -#define CLKID_SYS_PLL_DCO			102
>>> -#define CLKID_GP0_PLL_DCO			103
>>> -#define CLKID_HIFI_PLL_DCO			104
>>> -#define CLKID_VPU_0_DIV				111
>>> -#define CLKID_VPU_1_DIV				114
>>> -#define CLKID_VAPB_0_DIV			118
>>> -#define CLKID_VAPB_1_DIV			121
>>> -#define CLKID_HDMI_PLL_DCO			125
>>> -#define CLKID_HDMI_PLL_OD			126
>>> -#define CLKID_HDMI_PLL_OD2			127
>>> -#define CLKID_VID_PLL_SEL			130
>>> -#define CLKID_VID_PLL_DIV			131
>>> -#define CLKID_VCLK_SEL				132
>>> -#define CLKID_VCLK2_SEL				133
>>> -#define CLKID_VCLK_INPUT			134
>>> -#define CLKID_VCLK2_INPUT			135
>>> -#define CLKID_VCLK_DIV				136
>>> -#define CLKID_VCLK2_DIV				137
>>> -#define CLKID_VCLK_DIV2_EN			140
>>> -#define CLKID_VCLK_DIV4_EN			141
>>> -#define CLKID_VCLK_DIV6_EN			142
>>> -#define CLKID_VCLK_DIV12_EN			143
>>> -#define CLKID_VCLK2_DIV2_EN			144
>>> -#define CLKID_VCLK2_DIV4_EN			145
>>> -#define CLKID_VCLK2_DIV6_EN			146
>>> -#define CLKID_VCLK2_DIV12_EN			147
>>> -#define CLKID_CTS_ENCI_SEL			158
>>> -#define CLKID_CTS_ENCP_SEL			159
>>> -#define CLKID_CTS_VDAC_SEL			160
>>> -#define CLKID_HDMI_TX_SEL			161
>>> -#define CLKID_HDMI_SEL				166
>>> -#define CLKID_HDMI_DIV				167
>>> -#define CLKID_MALI_0_DIV			170
>>> -#define CLKID_MALI_1_DIV			173
>>> -#define CLKID_MPLL_50M_DIV			176
>>> -#define CLKID_SYS_PLL_DIV16_EN			178
>>> -#define CLKID_SYS_PLL_DIV16			179
>>> -#define CLKID_CPU_CLK_DYN0_SEL			180
>>> -#define CLKID_CPU_CLK_DYN0_DIV			181
>>> -#define CLKID_CPU_CLK_DYN0			182
>>> -#define CLKID_CPU_CLK_DYN1_SEL			183
>>> -#define CLKID_CPU_CLK_DYN1_DIV			184
>>> -#define CLKID_CPU_CLK_DYN1			185
>>> -#define CLKID_CPU_CLK_DYN			186
>>> -#define CLKID_CPU_CLK_DIV16_EN			188
>>> -#define CLKID_CPU_CLK_DIV16			189
>>> -#define CLKID_CPU_CLK_APB_DIV			190
>>> -#define CLKID_CPU_CLK_APB			191
>>> -#define CLKID_CPU_CLK_ATB_DIV			192
>>> -#define CLKID_CPU_CLK_ATB			193
>>> -#define CLKID_CPU_CLK_AXI_DIV			194
>>> -#define CLKID_CPU_CLK_AXI			195
>>> -#define CLKID_CPU_CLK_TRACE_DIV			196
>>> -#define CLKID_CPU_CLK_TRACE			197
>>> -#define CLKID_PCIE_PLL_DCO			198
>>> -#define CLKID_PCIE_PLL_DCO_DIV2			199
>>> -#define CLKID_PCIE_PLL_OD			200
>>> -#define CLKID_VDEC_1_SEL			202
>>> -#define CLKID_VDEC_1_DIV			203
>>> -#define CLKID_VDEC_HEVC_SEL			205
>>> -#define CLKID_VDEC_HEVC_DIV			206
>>> -#define CLKID_VDEC_HEVCF_SEL			208
>>> -#define CLKID_VDEC_HEVCF_DIV			209
>>> -#define CLKID_TS_DIV				211
>>> -#define CLKID_SYS1_PLL_DCO			213
>>> -#define CLKID_SYS1_PLL				214
>>> -#define CLKID_SYS1_PLL_DIV16_EN			215
>>> -#define CLKID_SYS1_PLL_DIV16			216
>>> -#define CLKID_CPUB_CLK_DYN0_SEL			217
>>> -#define CLKID_CPUB_CLK_DYN0_DIV			218
>>> -#define CLKID_CPUB_CLK_DYN0			219
>>> -#define CLKID_CPUB_CLK_DYN1_SEL			220
>>> -#define CLKID_CPUB_CLK_DYN1_DIV			221
>>> -#define CLKID_CPUB_CLK_DYN1			222
>>> -#define CLKID_CPUB_CLK_DYN			223
>>> -#define CLKID_CPUB_CLK_DIV16_EN			225
>>> -#define CLKID_CPUB_CLK_DIV16			226
>>> -#define CLKID_CPUB_CLK_DIV2			227
>>> -#define CLKID_CPUB_CLK_DIV3			228
>>> -#define CLKID_CPUB_CLK_DIV4			229
>>> -#define CLKID_CPUB_CLK_DIV5			230
>>> -#define CLKID_CPUB_CLK_DIV6			231
>>> -#define CLKID_CPUB_CLK_DIV7			232
>>> -#define CLKID_CPUB_CLK_DIV8			233
>>> -#define CLKID_CPUB_CLK_APB_SEL			234
>>> -#define CLKID_CPUB_CLK_APB			235
>>> -#define CLKID_CPUB_CLK_ATB_SEL			236
>>> -#define CLKID_CPUB_CLK_ATB			237
>>> -#define CLKID_CPUB_CLK_AXI_SEL			238
>>> -#define CLKID_CPUB_CLK_AXI			239
>>> -#define CLKID_CPUB_CLK_TRACE_SEL		240
>>> -#define CLKID_CPUB_CLK_TRACE			241
>>> -#define CLKID_GP1_PLL_DCO			242
>>> -#define CLKID_DSU_CLK_DYN0_SEL			244
>>> -#define CLKID_DSU_CLK_DYN0_DIV			245
>>> -#define CLKID_DSU_CLK_DYN0			246
>>> -#define CLKID_DSU_CLK_DYN1_SEL			247
>>> -#define CLKID_DSU_CLK_DYN1_DIV			248
>>> -#define CLKID_DSU_CLK_DYN1			249
>>> -#define CLKID_DSU_CLK_DYN			250
>>> -#define CLKID_DSU_CLK_FINAL			251
>>> -#define CLKID_SPICC0_SCLK_SEL			256
>>> -#define CLKID_SPICC0_SCLK_DIV			257
>>> -#define CLKID_SPICC1_SCLK_SEL			259
>>> -#define CLKID_SPICC1_SCLK_DIV			260
>>> -#define CLKID_NNA_AXI_CLK_SEL			262
>>> -#define CLKID_NNA_AXI_CLK_DIV			263
>>> -#define CLKID_NNA_CORE_CLK_SEL			265
>>> -#define CLKID_NNA_CORE_CLK_DIV			266
>>> -#define CLKID_MIPI_DSI_PXCLK_DIV		268
>>> +#define CLKID_PRIV_MPEG_SEL			8
>>> +#define CLKID_PRIV_MPEG_DIV			9
>>> +#define CLKID_PRIV_SD_EMMC_A_CLK0_SEL		63
>>> +#define CLKID_PRIV_SD_EMMC_A_CLK0_DIV		64
>>> +#define CLKID_PRIV_SD_EMMC_B_CLK0_SEL		65
>>> +#define CLKID_PRIV_SD_EMMC_B_CLK0_DIV		66
>>> +#define CLKID_PRIV_SD_EMMC_C_CLK0_SEL		67
>>> +#define CLKID_PRIV_SD_EMMC_C_CLK0_DIV		68
>>> +#define CLKID_PRIV_MPLL0_DIV			69
>>> +#define CLKID_PRIV_MPLL1_DIV			70
>>> +#define CLKID_PRIV_MPLL2_DIV			71
>>> +#define CLKID_PRIV_MPLL3_DIV			72
>>> +#define CLKID_PRIV_MPLL_PREDIV			73
>>> +#define CLKID_PRIV_FCLK_DIV2_DIV		75
>>> +#define CLKID_PRIV_FCLK_DIV3_DIV		76
>>> +#define CLKID_PRIV_FCLK_DIV4_DIV		77
>>> +#define CLKID_PRIV_FCLK_DIV5_DIV		78
>>> +#define CLKID_PRIV_FCLK_DIV7_DIV		79
>>> +#define CLKID_PRIV_FCLK_DIV2P5_DIV		100
>>> +#define CLKID_PRIV_FIXED_PLL_DCO		101
>>> +#define CLKID_PRIV_SYS_PLL_DCO			102
>>> +#define CLKID_PRIV_GP0_PLL_DCO			103
>>> +#define CLKID_PRIV_HIFI_PLL_DCO			104
>>> +#define CLKID_PRIV_VPU_0_DIV			111
>>> +#define CLKID_PRIV_VPU_1_DIV			114
>>> +#define CLKID_PRIV_VAPB_0_DIV			118
>>> +#define CLKID_PRIV_VAPB_1_DIV			121
>>> +#define CLKID_PRIV_HDMI_PLL_DCO			125
>>> +#define CLKID_PRIV_HDMI_PLL_OD			126
>>> +#define CLKID_PRIV_HDMI_PLL_OD2			127
>>> +#define CLKID_PRIV_VID_PLL_SEL			130
>>> +#define CLKID_PRIV_VID_PLL_DIV			131
>>> +#define CLKID_PRIV_VCLK_SEL			132
>>> +#define CLKID_PRIV_VCLK2_SEL			133
>>> +#define CLKID_PRIV_VCLK_INPUT			134
>>> +#define CLKID_PRIV_VCLK2_INPUT			135
>>> +#define CLKID_PRIV_VCLK_DIV			136
>>> +#define CLKID_PRIV_VCLK2_DIV			137
>>> +#define CLKID_PRIV_VCLK_DIV2_EN			140
>>> +#define CLKID_PRIV_VCLK_DIV4_EN			141
>>> +#define CLKID_PRIV_VCLK_DIV6_EN			142
>>> +#define CLKID_PRIV_VCLK_DIV12_EN		143
>>> +#define CLKID_PRIV_VCLK2_DIV2_EN		144
>>> +#define CLKID_PRIV_VCLK2_DIV4_EN		145
>>> +#define CLKID_PRIV_VCLK2_DIV6_EN		146
>>> +#define CLKID_PRIV_VCLK2_DIV12_EN		147
>>> +#define CLKID_PRIV_CTS_ENCI_SEL			158
>>> +#define CLKID_PRIV_CTS_ENCP_SEL			159
>>> +#define CLKID_PRIV_CTS_VDAC_SEL			160
>>> +#define CLKID_PRIV_HDMI_TX_SEL			161
>>> +#define CLKID_PRIV_HDMI_SEL			166
>>> +#define CLKID_PRIV_HDMI_DIV			167
>>> +#define CLKID_PRIV_MALI_0_DIV			170
>>> +#define CLKID_PRIV_MALI_1_DIV			173
>>> +#define CLKID_PRIV_MPLL_50M_DIV			176
>>> +#define CLKID_PRIV_SYS_PLL_DIV16_EN		178
>>> +#define CLKID_PRIV_SYS_PLL_DIV16		179
>>> +#define CLKID_PRIV_CPU_CLK_DYN0_SEL		180
>>> +#define CLKID_PRIV_CPU_CLK_DYN0_DIV		181
>>> +#define CLKID_PRIV_CPU_CLK_DYN0			182
>>> +#define CLKID_PRIV_CPU_CLK_DYN1_SEL		183
>>> +#define CLKID_PRIV_CPU_CLK_DYN1_DIV		184
>>> +#define CLKID_PRIV_CPU_CLK_DYN1			185
>>> +#define CLKID_PRIV_CPU_CLK_DYN			186
>>> +#define CLKID_PRIV_CPU_CLK_DIV16_EN		188
>>> +#define CLKID_PRIV_CPU_CLK_DIV16		189
>>> +#define CLKID_PRIV_CPU_CLK_APB_DIV		190
>>> +#define CLKID_PRIV_CPU_CLK_APB			191
>>> +#define CLKID_PRIV_CPU_CLK_ATB_DIV		192
>>> +#define CLKID_PRIV_CPU_CLK_ATB			193
>>> +#define CLKID_PRIV_CPU_CLK_AXI_DIV		194
>>> +#define CLKID_PRIV_CPU_CLK_AXI			195
>>> +#define CLKID_PRIV_CPU_CLK_TRACE_DIV		196
>>> +#define CLKID_PRIV_CPU_CLK_TRACE		197
>>> +#define CLKID_PRIV_PCIE_PLL_DCO			198
>>> +#define CLKID_PRIV_PCIE_PLL_DCO_DIV2		199
>>> +#define CLKID_PRIV_PCIE_PLL_OD			200
>>> +#define CLKID_PRIV_VDEC_1_SEL			202
>>> +#define CLKID_PRIV_VDEC_1_DIV			203
>>> +#define CLKID_PRIV_VDEC_HEVC_SEL		205
>>> +#define CLKID_PRIV_VDEC_HEVC_DIV		206
>>> +#define CLKID_PRIV_VDEC_HEVCF_SEL		208
>>> +#define CLKID_PRIV_VDEC_HEVCF_DIV		209
>>> +#define CLKID_PRIV_TS_DIV			211
>>> +#define CLKID_PRIV_SYS1_PLL_DCO			213
>>> +#define CLKID_PRIV_SYS1_PLL			214
>>> +#define CLKID_PRIV_SYS1_PLL_DIV16_EN		215
>>> +#define CLKID_PRIV_SYS1_PLL_DIV16		216
>>> +#define CLKID_PRIV_CPUB_CLK_DYN0_SEL		217
>>> +#define CLKID_PRIV_CPUB_CLK_DYN0_DIV		218
>>> +#define CLKID_PRIV_CPUB_CLK_DYN0		219
>>> +#define CLKID_PRIV_CPUB_CLK_DYN1_SEL		220
>>> +#define CLKID_PRIV_CPUB_CLK_DYN1_DIV		221
>>> +#define CLKID_PRIV_CPUB_CLK_DYN1		222
>>> +#define CLKID_PRIV_CPUB_CLK_DYN			223
>>> +#define CLKID_PRIV_CPUB_CLK_DIV16_EN		225
>>> +#define CLKID_PRIV_CPUB_CLK_DIV16		226
>>> +#define CLKID_PRIV_CPUB_CLK_DIV2		227
>>> +#define CLKID_PRIV_CPUB_CLK_DIV3		228
>>> +#define CLKID_PRIV_CPUB_CLK_DIV4		229
>>> +#define CLKID_PRIV_CPUB_CLK_DIV5		230
>>> +#define CLKID_PRIV_CPUB_CLK_DIV6		231
>>> +#define CLKID_PRIV_CPUB_CLK_DIV7		232
>>> +#define CLKID_PRIV_CPUB_CLK_DIV8		233
>>> +#define CLKID_PRIV_CPUB_CLK_APB_SEL		234
>>> +#define CLKID_PRIV_CPUB_CLK_APB			235
>>> +#define CLKID_PRIV_CPUB_CLK_ATB_SEL		236
>>> +#define CLKID_PRIV_CPUB_CLK_ATB			237
>>> +#define CLKID_PRIV_CPUB_CLK_AXI_SEL		238
>>> +#define CLKID_PRIV_CPUB_CLK_AXI			239
>>> +#define CLKID_PRIV_CPUB_CLK_TRACE_SEL		240
>>> +#define CLKID_PRIV_CPUB_CLK_TRACE		241
>>> +#define CLKID_PRIV_GP1_PLL_DCO			242
>>> +#define CLKID_PRIV_DSU_CLK_DYN0_SEL		244
>>> +#define CLKID_PRIV_DSU_CLK_DYN0_DIV		245
>>> +#define CLKID_PRIV_DSU_CLK_DYN0			246
>>> +#define CLKID_PRIV_DSU_CLK_DYN1_SEL		247
>>> +#define CLKID_PRIV_DSU_CLK_DYN1_DIV		248
>>> +#define CLKID_PRIV_DSU_CLK_DYN1			249
>>> +#define CLKID_PRIV_DSU_CLK_DYN			250
>>> +#define CLKID_PRIV_DSU_CLK_FINAL		251
>>> +#define CLKID_PRIV_SPICC0_SCLK_SEL		256
>>> +#define CLKID_PRIV_SPICC0_SCLK_DIV		257
>>> +#define CLKID_PRIV_SPICC1_SCLK_SEL		259
>>> +#define CLKID_PRIV_SPICC1_SCLK_DIV		260
>>> +#define CLKID_PRIV_NNA_AXI_CLK_SEL		262
>>> +#define CLKID_PRIV_NNA_AXI_CLK_DIV		263
>>> +#define CLKID_PRIV_NNA_CORE_CLK_SEL		265
>>> +#define CLKID_PRIV_NNA_CORE_CLK_DIV		266
>>> +#define CLKID_PRIV_MIPI_DSI_PXCLK_DIV		268
>>>     #define NR_CLKS					271
>>

Neil Armstrong June 1, 2023, 2:12 p.m. UTC | #7

Hi,

On Tue, 30 May 2023 09:38:01 +0200, Neil Armstrong wrote:
> The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a),
> with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI
> glue on the same Amlogic SoCs.
> 
> This adds support for the glue managing the transceiver, mimicing the init flow provided
> by Amlogic to setup the ENCL encoder, the glue, the transceiver, the digital D-PHY and the
> Analog PHY in the proper way.
> 
> [...]

Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git (drm-misc-next)

[06/17] dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings
        https://cgit.freedesktop.org/drm/drm-misc/commit/?id=0628f2341e96213c9f2d074853b255f65acd3795
[07/17] dt-bindings: display: meson-vpu: add third DPI output port
        https://cgit.freedesktop.org/drm/drm-misc/commit/?id=25b3b35cd51ef0d98165666d250a51f39db6a1fc
[08/17] drm/meson: fix unbind path if HDMI fails to bind
        https://cgit.freedesktop.org/drm/drm-misc/commit/?id=6a044642988b5f8285f3173b8e88784bef2bc306
[09/17] drm/meson: only use components with dw-hdmi
        https://cgit.freedesktop.org/drm/drm-misc/commit/?id=44e16166e0e9b94d8bcdf55fc0e5fcceca1154f0
[10/17] drm/meson: venc: add ENCL encoder setup for MIPI-DSI output
        https://cgit.freedesktop.org/drm/drm-misc/commit/?id=51fc01a03442cce5e4c21375a1ceb2e4ec93c833
[11/17] drm/meson: add DSI encoder
        https://cgit.freedesktop.org/drm/drm-misc/commit/?id=42dcf15f901c8222352da31d622b4ee844068f42
[12/17] drm/meson: add support for MIPI-DSI transceiver
        https://cgit.freedesktop.org/drm/drm-misc/commit/?id=77d9e1e6b8468f701ab024a060aa9c0339356870
[13/17] drm/panel: khadas-ts050: update timings to achieve 60Hz refresh rate
        https://cgit.freedesktop.org/drm/drm-misc/commit/?id=29c6df0d942454cb43334cf0e36de068f4124b94