| Message ID | 20230603025035.3781797-1-reijiw@google.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | KVM: arm64: PMU: Correct the handling of PMUSERENR_EL0 | expand |
On Fri, 2 Jun 2023 19:50:33 -0700, Reiji Watanabe wrote: > This series will fix bugs in KVM's handling of PMUSERENR_EL0. > > With PMU access support from EL0 [1], the perf subsystem would > set CR and ER bits of PMUSERENR_EL0 as needed to allow EL0 to have > a direct access to PMU counters. However, KVM appears to assume > that the register value is always zero for the host EL0, and has > the following two problems in handling the register. > > [...] Applied to fixes, thanks! [1/2] KVM: arm64: PMU: Restore the host's PMUSERENR_EL0 commit: 8681f71759010503892f9e3ddb05f65c0f21b690 [2/2] KVM: arm64: PMU: Don't overwrite PMUSERENR with vcpu loaded commit: 0c2f9acf6ae74118385f7a7d48f4b2d93637b628 Cheers, M.
This series will fix bugs in KVM's handling of PMUSERENR_EL0. With PMU access support from EL0 [1], the perf subsystem would set CR and ER bits of PMUSERENR_EL0 as needed to allow EL0 to have a direct access to PMU counters. However, KVM appears to assume that the register value is always zero for the host EL0, and has the following two problems in handling the register. [A] The host EL0 might lose the direct access to PMU counters, as KVM always clears PMUSERENR_EL0 before returning to userspace. [B] With VHE, the guest EL0 access to PMU counters might be trapped to EL1 instead of to EL2 (even when PMUSERENR_EL0 for the guest indicates that the guest EL0 has an access to the counters). This is because, with VHE, KVM sets ER, CR, SW and EN bits of PMUSERENR_EL0 to 1 on vcpu_load() to ensure to trap PMU access from the guset EL0 to EL2, but those bits might be cleared by the perf subsystem after vcpu_load() (when PMU counters are programmed for the vPMU emulation). Patch-1 will fix [A], and Patch-2 will fix [B] respectively. The series is based on 6.4-rc4. v5: - Move IRQ save/restore to {activate,deactivate}_traps_vhe_{load,put}(). v4: https://lore.kernel.org/all/20230416045316.1367849-1-reijiw@google.com/ - Introduce NO_DEBUG_IRQFLAGS to exclude warn_bogus_irq_restore() from the nVHE hyp code. This is to address the issue [2] that was reported by kernel test robot <lkp@intel.com>. v3: https://lore.kernel.org/all/20230415164029.526895-1-reijiw@google.com/ - While vcpu_{put,load}() are manipulating PMUSERENR_EL0, disable IRQs to prevent a race condition between these processes and IPIs that updates PMUSERENR_EL0. [Mark] v2: https://lore.kernel.org/all/20230408034759.2369068-1-reijiw@google.com/ - Save the PMUSERENR_EL0 for the host in the sysreg array of kvm_host_data. [Marc] - Don't let armv8pmu_start() overwrite PMUSERENR if the vCPU is loaded, instead have KVM update the saved shadow register value for the host. [Marc, Mark] v1: https://lore.kernel.org/all/20230329002136.2463442-1-reijiw@google.com/ [1] https://github.com/torvalds/linux/commit/83a7a4d643d33a8b74a42229346b7ed7139fcef9 [2] https://lore.kernel.org/all/202304160658.Oqr1xZbi-lkp@intel.com/ Reiji Watanabe (2): KVM: arm64: PMU: Restore the host's PMUSERENR_EL0 KVM: arm64: PMU: Don't overwrite PMUSERENR with vcpu loaded arch/arm/include/asm/arm_pmuv3.h | 5 +++++ arch/arm64/include/asm/kvm_host.h | 7 +++++++ arch/arm64/kvm/hyp/include/hyp/switch.h | 15 ++++++++++++-- arch/arm64/kvm/hyp/vhe/switch.c | 14 +++++++++++++ arch/arm64/kvm/pmu.c | 27 +++++++++++++++++++++++++ drivers/perf/arm_pmuv3.c | 21 ++++++++++++++++--- 6 files changed, 84 insertions(+), 5 deletions(-) base-commit: 7877cb91f1081754a1487c144d85dc0d2e2e7fc4