From patchwork Sat Jun 3 02:50:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13266053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 408CEC7EE2A for ; Sat, 3 Jun 2023 02:51:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: Mime-Version:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=PJJ0CpjUd/BhDFGnmqLVTIO9GXp0hRC4Suiwl+sbcOA=; b=YTW Zwdapboa/isSwDdoHwp0DAhcZNafiR/sd5L6eg6TwvmKXsu35bSIm4hSpjjpyJ9TObRmHcgrIwaU6 VOB+ISXnsHUQmIX7VNW1qV9kP3WOEQHwKCqZd3ybXsbQfjukp/X0St1tXSAnNgFaK9M1NWaq9uPvu haMTsk9gkHWfB10fQiJpIm00lPr4ZXAwJCS0AhPYZL15NEaDsYNMBq3LEfvQm72szBuDUZRK6HO9P +OWGGO1CfE/g5VNONdzmwq9uk3eXhsA9oqWQ6d/S4E25e2HLGpBk4gvRnah5mFYDU0mcEK5PsmWhE vh+De3h7SUGXX/5HuwvKuxGtXFgpSdA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q5HM6-008aJC-2T; Sat, 03 Jun 2023 02:51:02 +0000 Received: from mail-yb1-xb4a.google.com ([2607:f8b0:4864:20::b4a]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q5HM2-008aIJ-2Y for linux-arm-kernel@lists.infradead.org; Sat, 03 Jun 2023 02:51:00 +0000 Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-bacd408046cso3917204276.3 for ; Fri, 02 Jun 2023 19:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685760656; x=1688352656; h=cc:to:from:subject:message-id:mime-version:date:from:to:cc:subject :date:message-id:reply-to; bh=UOf7JPRrL9hOlCaj9LUz9Ny3KjSPlKOPu6lXUFM6n9A=; b=xkSOr8wPdu2X1Ygw948lyPjL5RZCQ2t2i9AMO19v/2eo1cDzHmh5ywh5RA7q5cJKzt 6HGicNi6fFQzgfPoHLvyOBh8clVCjQZqwgqrIZIxVGZtCtdwKpnHqP+Fq8eKCpkpmR2e N5RCdxzXmZdCEyrt1qxBg6UBMcjOmvCAgb0STUfw6Evfvw7cOTKPYu+hZ47vWL2BfoMi YcsSmW8Lwqzd/jx7NHUtN8OJqA2PMc3I2vo8Zdjq54G+oW/HgJRXoYR8UhgTXWrKQPf+ XwPiySuX0KRWbQoj6hG4yDWEeSaXik+gpix2RPSc/vje5IkSCGFz+XZjVf0gLUHHelCD BeIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685760656; x=1688352656; h=cc:to:from:subject:message-id:mime-version:date:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=UOf7JPRrL9hOlCaj9LUz9Ny3KjSPlKOPu6lXUFM6n9A=; b=AyjA1lhKzDyjdgUty0ql5JSeOvC/4YeMWUev3OypvajtRGk0XvgWSb0l9+racu19HG 38HV+vZOLPh/m15V4Oo1K3iw7DNdhLsPJyMBSU9ibxGwV3N06cUn+x93RdVujWw5fjcH MzcFhqAzRHDHxWITqu+QpTL4HwKnv9SwxxkO4JkwtGw7E6QJUy80qULA7+lG0kdeNarG lFujVovPN8c6nvkwAMmm/XPIj/rs5bt+FPL82mJZsIHG4f8w08oK/7S+DhcEJJ27ONPS TJAIcJVQdohu2ATNS7AP/pv0lg0GAn8xcKSjGGmWd1Sin9kb+W7Lj3M5qSfUfj0tOukR i8Sw== X-Gm-Message-State: AC+VfDyml4RCHrFT9v4DKcMdUHIG2TktewfrVLflqvYp1cbGnXVNrUrj UrbB+hUeViY50/580L2K9OMCjPrjskA= X-Google-Smtp-Source: ACHHUZ4nr7cemm/IrLIW9GYN15UjE/9E42hV5mDDFqDGx7aWoU9woHyAtb3GzYQn3XbU4w1OfNQQzKwbR3Q= X-Received: from reijiw-west4.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:aa1]) (user=reijiw job=sendgmr) by 2002:a05:6902:100a:b0:bad:600:1833 with SMTP id w10-20020a056902100a00b00bad06001833mr2835309ybt.0.1685760656190; Fri, 02 Jun 2023 19:50:56 -0700 (PDT) Date: Fri, 2 Jun 2023 19:50:33 -0700 Mime-Version: 1.0 X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog Message-ID: <20230603025035.3781797-1-reijiw@google.com> Subject: [PATCH v5 0/2] KVM: arm64: PMU: Correct the handling of PMUSERENR_EL0 From: Reiji Watanabe To: Marc Zyngier , Mark Rutland , Oliver Upton , Will Deacon , Catalin Marinas , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Shaoqin Huang , Rob Herring , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230602_195058_874118_A8ACA554 X-CRM114-Status: GOOD ( 14.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series will fix bugs in KVM's handling of PMUSERENR_EL0. With PMU access support from EL0 [1], the perf subsystem would set CR and ER bits of PMUSERENR_EL0 as needed to allow EL0 to have a direct access to PMU counters. However, KVM appears to assume that the register value is always zero for the host EL0, and has the following two problems in handling the register. [A] The host EL0 might lose the direct access to PMU counters, as KVM always clears PMUSERENR_EL0 before returning to userspace. [B] With VHE, the guest EL0 access to PMU counters might be trapped to EL1 instead of to EL2 (even when PMUSERENR_EL0 for the guest indicates that the guest EL0 has an access to the counters). This is because, with VHE, KVM sets ER, CR, SW and EN bits of PMUSERENR_EL0 to 1 on vcpu_load() to ensure to trap PMU access from the guset EL0 to EL2, but those bits might be cleared by the perf subsystem after vcpu_load() (when PMU counters are programmed for the vPMU emulation). Patch-1 will fix [A], and Patch-2 will fix [B] respectively. The series is based on 6.4-rc4. v5: - Move IRQ save/restore to {activate,deactivate}_traps_vhe_{load,put}(). v4: https://lore.kernel.org/all/20230416045316.1367849-1-reijiw@google.com/ - Introduce NO_DEBUG_IRQFLAGS to exclude warn_bogus_irq_restore() from the nVHE hyp code. This is to address the issue [2] that was reported by kernel test robot . v3: https://lore.kernel.org/all/20230415164029.526895-1-reijiw@google.com/ - While vcpu_{put,load}() are manipulating PMUSERENR_EL0, disable IRQs to prevent a race condition between these processes and IPIs that updates PMUSERENR_EL0. [Mark] v2: https://lore.kernel.org/all/20230408034759.2369068-1-reijiw@google.com/ - Save the PMUSERENR_EL0 for the host in the sysreg array of kvm_host_data. [Marc] - Don't let armv8pmu_start() overwrite PMUSERENR if the vCPU is loaded, instead have KVM update the saved shadow register value for the host. [Marc, Mark] v1: https://lore.kernel.org/all/20230329002136.2463442-1-reijiw@google.com/ [1] https://github.com/torvalds/linux/commit/83a7a4d643d33a8b74a42229346b7ed7139fcef9 [2] https://lore.kernel.org/all/202304160658.Oqr1xZbi-lkp@intel.com/ Reiji Watanabe (2): KVM: arm64: PMU: Restore the host's PMUSERENR_EL0 KVM: arm64: PMU: Don't overwrite PMUSERENR with vcpu loaded arch/arm/include/asm/arm_pmuv3.h | 5 +++++ arch/arm64/include/asm/kvm_host.h | 7 +++++++ arch/arm64/kvm/hyp/include/hyp/switch.h | 15 ++++++++++++-- arch/arm64/kvm/hyp/vhe/switch.c | 14 +++++++++++++ arch/arm64/kvm/pmu.c | 27 +++++++++++++++++++++++++ drivers/perf/arm_pmuv3.c | 21 ++++++++++++++++--- 6 files changed, 84 insertions(+), 5 deletions(-) base-commit: 7877cb91f1081754a1487c144d85dc0d2e2e7fc4