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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id x1-20020a5d54c1000000b003176f2d9ce5sm18338098wrv.71.2023.08.02.01.04.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 01:04:01 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , =?utf-8?q?R=C3=A9mi_Denis-Courmont?= , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti Subject: [PATCH v6 00/10] riscv: Allow userspace to directly access perf counters Date: Wed, 2 Aug 2023 10:03:18 +0200 Message-Id: <20230802080328.1213905-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230802_010403_912342_71A5056A X-CRM114-Status: GOOD ( 18.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org riscv used to allow direct access to cycle/time/instret counters, bypassing the perf framework, this patchset intends to allow the user to mmap any counter when accessed through perf. **Important**: The default mode is now user access through perf only, not the legacy so some applications will break. However, we introduce a sysctl perf_user_access like arm64 does, which will allow to switch to the legacy mode described above. This version needs openSBI v1.3 *and* a kernel fix that went upstream lately (https://lore.kernel.org/lkml/20230616114831.3186980-1-maz@kernel.org/T/). base-commit-tag: v6.5-rc1 Changes in v6: - Replaced csr_read() preprocessor parsing of csr number with the input constraint, as suggested by Ian - Added a defined(__riscv) and a comment to make things clearer, as suggested by Ian Changes in v5: - Fix typo from Atish - Add RB from Atish and Andrew - Improve cover letter and patch 7 commit log to explain why we made the choice to break userspace for security reasons, thanks Atish and Rémi - Rebase on top of v6.5-rc1 Changes in v4: - Fixed some nits in riscv_pmu_sbi.c thanks to Andrew - Fixed the documentation thanks to Andrew - Added RB from Andrew \o/ Changes in v3: - patch 1 now contains the ref to the faulty commit (no Fixes tag as it is only a comment), as Andrew suggested - Removed RISCV_PMU_LEGACY_TIME from patch 3, as Andrew suggested - Rename RISCV_PMU_PDEV_NAME to "riscv-pmu-sbi", patch4 is just cosmetic now, as Andrew suggested - Removed a few useless (and wrong) comments, as Andrew suggested - Simplify arch_perf_update_userpage code, as Andrew suggested - Documentation now mentions that time CSR is *always* accessible, whatever the mode, as suggested by Andrew - Removed CYCLEH reference and add TODO for rv32 support, as suggested by Atish - Do not rename the pmu instance as Atish suggested - Set pmc_width only if rdpmc is enabled and CONFIG_RISCV_PMU is set and the event is a hw event - Move arch_perf_update_userpage https://lore.kernel.org/lkml/20230616114831.3186980-1-maz@kernel.org/T/ - **Switch to user mode access by default** Changes in v2: - Split into smaller patches, way better! - Add RB from Conor - Simplify the way we checked riscv architecture - Fix race mmap and other thread running on other cpus - Use hwc when available - Set all userspace access flags in event_init, too cumbersome to handle sysctl changes - Fix arch_perf_update_userpage for pmu other than riscv-pmu by renaming pmu driver - Fixed kernel test robot build error - Fixed documentation (Andrew and Bagas) - perf testsuite passes mmap tests in all 3 modes Alexandre Ghiti (10): perf: Fix wrong comment about default event_idx include: riscv: Fix wrong include guard in riscv_pmu.h riscv: Make legacy counter enum match the HW numbering drivers: perf: Rename riscv pmu sbi driver riscv: Prepare for user-space perf event mmap support drivers: perf: Implement perf event mmap support in the legacy backend drivers: perf: Implement perf event mmap support in the SBI backend Documentation: admin-guide: Add riscv sysctl_perf_user_access tools: lib: perf: Implement riscv mmap support perf: tests: Adapt mmap-basic.c for riscv Documentation/admin-guide/sysctl/kernel.rst | 27 ++- drivers/perf/riscv_pmu.c | 113 +++++++++++ drivers/perf/riscv_pmu_legacy.c | 28 ++- drivers/perf/riscv_pmu_sbi.c | 196 +++++++++++++++++++- include/linux/perf/riscv_pmu.h | 12 +- include/linux/perf_event.h | 3 +- tools/lib/perf/mmap.c | 66 +++++++ tools/perf/tests/mmap-basic.c | 6 +- 8 files changed, 431 insertions(+), 20 deletions(-)