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Wed, 20 Sep 2023 12:28:17 -0700 (PDT) Received: from localhost ([85.140.6.205]) by smtp.gmail.com with ESMTPSA id t26-20020ac2549a000000b004fe09e6d1e7sm2785403lfk.110.2023.09.20.12.28.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:28:16 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 00/18] EDAC/synopsys: Add generic DDRC info and address mapping Date: Wed, 20 Sep 2023 22:26:45 +0300 Message-ID: <20230920192806.29960-1-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230920_122819_614875_38A36D93 X-CRM114-Status: GOOD ( 26.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patchset is a second one in the series created in the framework of my Synopsys DW uMCTL2 DDRC-related work: [1: In-progress v4] EDAC/mc/synopsys: Various fixes and cleanups Link: https://lore.kernel.org/linux-edac/20230920191059.28395-1-fancer.lancer@gmail.com [2: In-progress v4] EDAC/synopsys: Add generic DDRC info and address mapping Link: ---you are looking at it--- [3: In-progress v4] EDAC/synopsys: Add generic resources and Scrub support Link: ---to be submitted--- Note the patchsets above must be merged in the same order as they are placed in the list in order to prevent conflicts. Nothing prevents them from being reviewed synchronously though. Any tests are very welcome. Thanks in advance. The second patchset mainly concerns converting the DW uMCTL2 DDRC driver to being more generic, supporting wider range of the DW uMCTL2 DDRC IP-core compilations and thus being utilized with more versions of the Synopsys DDR controllers. The series starts with the Error-injection functionality movement to DebugFS. Indeed the Debug-parts should be in the dedicated DebugFS. SysFS is not a place for it. Moreover a bit later here some more debug nodes will be added. Afterwards even though it isn't advertised but even at this stage the DW uMCTL2 DDRC driver supports a bit more DDR protocols than it is actually specified in the mem_ctrl_info.mtype_cap field. So first the EDAC MCI core memory types enumeration is extended with LPDDR (mDDR) and LPDDR2, which support can be enabled in the DW uMCTL2 DDR controller. Second the driver is fixed to properly detected the new and older DDR protocol types during the DW uMCTL DDRC probe procedure. Then a bit painful patch goes. Alas we have to deviate the driver from the EDAC standard private data allocation/initialization pattern. Since we are going to add the DW uMCTL2 IP-core specific parameters detection procedure and later on implement additional platform resources requests, there is no other choice but to allocate the driver private data at the early stage of the device probe procedure, even before it's possible to allocate the MCI descriptor. The DW uMCTL2 DDRC platform resources and configuration info will be then utilized to properly allocate and initialize the mem_ctrl_info structure instance. Fifth patch in the series is very important. It provides the DW uMCTL2 DDRC parameters detection procedure. The DDRC and ECC parameters detected at this stage will be then utilized to make the driver working with much wider set of the DW uMCTL2 revisions and configurations. In particular from now the driver will retrieve the next DDRC info at the probe stage: ECC type, SDRAM protocol (DDR type), Full and actual DQ-bus width, SDRAM and HIF burst length, Core/SDRAM frequency ration, number of SDRAM ranks. The DDRC parameters structure will be extended with some more fields later in this and the next patchset. The provided private DDRC parameters infrastructure can be utilized to implement the platform-specific capabilities so the platform data and its quirks are replaced with it. The detected at the probe stage DW uMCTL2 DDRC parameters can be now used to implement the configuration specific functionality. In particular first we introduce the conditional ADDRMAP* CSRs parsing since some of these CSRs and their fields are left unused by the controller in some cases. Secondly actual DIMM ECC errors grain, ECC corrected bit, syndrome and full data+ecc pattern are determined based on the DDRC parameters. Afterwards goes a series of the patches which introduce an interface to generically determine the system address based on the SDRAM address and vice-versa. Thus we'll be able to report actual PFN and offset in case of the corrected and uncorrected errors. So first we get to convert the currently available HIF/SDRAM mapping table utilized for the errors-injection functionality into a more generic Sys<->SDRAM address translation interface. Secondly we suggest to conform the SDRAM column address mapping detection algorithm with what is defined in the DW uMCTL2 DDRC hw reference manual thus simplifying the ADDRMAP* CSRs parsing procedure. After adding a handy DebugFS node to read the HIF/SDRAM mapping and the system address regions support, we finally introduce the erroneous page-frame/offset reporting to the MCI core. Since the full SDRAM address mapping is now always available we suggest to use it for the attached memory size calculation, which is a more correct approach rather than the si_meminfo()-based one. Changelog v2: - Rebase onto the latest version of the patchset: [PATCH v2 00/19] EDAC/mc/synopsys: Various fixes and cleanups - Just resend. Changelog v3: - Just resend. Changelog v4: - Get syndrome from the ECCSTAT.ecc_corrected_bit_num field rather than from ECCCSYN2. The later CSR in fact contains ECC. - On correctable and uncorrectable errors retrieve ECC aside with the erroneous data. - Rebase onto the kernel v6.6-rcX. Signed-off-by: Serge Semin Cc: Punnaiah Choudary Kalluri Cc: Dinh Nguyen Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org Serge Semin (18): EDAC/synopsys: Convert sysfs nodes to debugfs ones EDAC/mc: Extend memtypes with LPDDR(mDDR) and LPDDR2 EDAC/synopsys: Extend memtypes supported by controller EDAC/synopsys: Detach private data from mci instance EDAC/synopsys: Add DDRC basic parameters infrastructure EDAC/synopsys: Convert plat-data to plat-init function EDAC/synopsys: Parse ADDRMAP[7-8] CSRs for (LP)DDR4 only EDAC/synopsys: Parse ADDRMAP[0] CSR for multi-ranks case only EDAC/synopsys: Set actual DIMM ECC errors grain EDAC/synopsys: Get corrected bit position EDAC/synopsys: Pass syndrome to EDAC error handler EDAC/synopsys: Read full data+ecc pattern on errors EDAC/synopsys: Introduce System/SDRAM address translation interface EDAC/synopsys: Simplify HIF/SDRAM column mapping get procedure EDAC/synopsys: Add HIF/SDRAM mapping debugfs node EDAC/synopsys: Add erroneous page-frame/offset reporting EDAC/synopsys: Add system address regions support EDAC/synopsys: Add mapping-based memory size calculation drivers/edac/edac_mc.c | 2 + drivers/edac/synopsys_edac.c | 1828 ++++++++++++++++++++++++---------- include/linux/edac.h | 6 + 3 files changed, 1321 insertions(+), 515 deletions(-)