From patchwork Tue Oct 10 12:30:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 13415331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C67AFCD80BD for ; Tue, 10 Oct 2023 12:34:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=pe8z+b+j4UWEjTMdlCrLKTL8Ez/IIIgXMsCxm/Vd/Qg=; b=GmhOFLGvlpAjKp TAkqYDQVk2RQvJSfHRp9QDabtMDvj+f+8tsGsDvvcWxMaCCNa7LRqZ8PUwX79SQsQ6aiOgbOIr0hz yKCTHg3Wn/Y2Iq5C7yAFPSiSyeNv2QiOZqT6MB1IhKbrQ6dvGtJse1rJoF4QhVEWa7K354i4kMkZH UQWvIlKSvzOoGLx7wXJT85lnhLJzYzW+XtrQe/HYZaqIN7y/CJRo7dbTSmvxI1JTWN4SDeHVkk306 xY/Q3OeKVcg/1Cn7ZMY6a3ymk2pEl4Zn08TsvQ1I6MEtbySzcyDRycdXLf4d4s61iThDETm1TWjKT MxMYO503zVuAiRFhIXIA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qqBvb-00DLf4-2U; Tue, 10 Oct 2023 12:33:35 +0000 Received: from szxga02-in.huawei.com ([45.249.212.188]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qqBvY-00DLcl-1W for linux-arm-kernel@lists.infradead.org; Tue, 10 Oct 2023 12:33:34 +0000 Received: from canpemm500009.china.huawei.com (unknown [172.30.72.56]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4S4Zwd3MMszVlR7; Tue, 10 Oct 2023 20:29:53 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Tue, 10 Oct 2023 20:33:21 +0800 From: Yicong Yang To: , , , CC: , , , , , , , , Subject: [RFC PATCH 0/3] Add HiSilicon system timer driver Date: Tue, 10 Oct 2023 20:30:30 +0800 Message-ID: <20231010123033.23258-1-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231010_053332_669374_9297A26F X-CRM114-Status: GOOD ( 10.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yicong Yang HiSilicon system timer is a memory mapped platform timer compatible with the arm's generic timer specification. The timer supports both SPI and LPI interrupt and can be enumerated through ACPI DSDT table. Since the timer is fully compatible with the spec, it can reuse most codes of the arm_arch_timer driver. However since the arm_arch_timer driver only supports GTDT and SPI interrupt, this series support the HiSilicon system timer by: - refactor some of the arm_arch_timer codes and export the function to register a arch memory timer by other drivers - retrieve the IO memory and interrupt resource through DSDT in a separate driver, then setup and register the clockevent device reuse the arm_arch_timer function Using LPI for the timer is mentioned in BSA Spec section 3.8.1 (DEN0094C 1.0C). Yicong Yang (3): clocksource/drivers/arm_arch_timer: Split the function of __arch_timer_setup() clocksource/drivers/arm_arch_timer: Extend and export arch_timer_mem_register() clocksource/drivers: Add HiSilicon system timer driver drivers/clocksource/Kconfig | 10 +++ drivers/clocksource/Makefile | 1 + drivers/clocksource/arm_arch_timer.c | 123 +++++++++++++++------------ drivers/clocksource/timer-hisi-sys.c | 68 +++++++++++++++ include/clocksource/arm_arch_timer.h | 2 + 5 files changed, 148 insertions(+), 56 deletions(-) create mode 100644 drivers/clocksource/timer-hisi-sys.c