From patchwork Tue Oct 17 05:23:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 13424445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3D1ACDB474 for ; Tue, 17 Oct 2023 05:24:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=jNrPw9wSA70p6EVXQGEx0fjMLyfnZscnanN0yWnLrkA=; b=SXX1X2V/FC/Dpd lXTU1DPQ4VxRLnuq6qFYitPDFqnP4JdWepFy4gcqmSrZt0F1IuEEPliIZ7amP6Wv/0S+81xjXGuOp L4SVth3z2cWKsKQv4wq3nP8LYdQqxLW2o0/6HApwWw7p5u6PemgDeSHPZNd/ekTE21jJctFMq+47J ive5UoQsCaAjg+I9eOFFYtn5CKSwjzEbZLGiUfx9/AttqgxF4TLGzvm2+k0foOTcnOkeYVshE6EUo 65P3GMhOIaWYx9VaKftPQkACxh0yb8bkpYx87WUvRInbILI720uUJE1Cr0visMNllD06QbulhtAse qph/XZ/ZvW83YrhNuwkQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qscYR-00BHYw-28; Tue, 17 Oct 2023 05:23:43 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qscYO-00BHXV-0a for linux-arm-kernel@lists.infradead.org; Tue, 17 Oct 2023 05:23:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6EE751FB; Mon, 16 Oct 2023 22:24:12 -0700 (PDT) Received: from u200865.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 98CD13F5A1; Mon, 16 Oct 2023 22:23:31 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, maz@kernel.org, anshuman.khandual@arm.com, krisman@suse.de, broonie@kernel.org, james.morse@arm.com, ionela.voinescu@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v2 0/3] arm64: cpufeatures: Display enabled cores Date: Tue, 17 Oct 2023 00:23:19 -0500 Message-ID: <20231017052322.1211099-1-jeremy.linton@arm.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231016_222340_292609_C7625F20 X-CRM114-Status: UNSURE ( 8.81 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The AMU feature can be enabled on a subset of the cores in a system. Because of that, it prints a message for each core as it is detected. This becomes tedious when there are hundreds of cores. Instead, for CPU features which can be enabled on a subset of the present cores, lets wait until update_cpu_capabilities() and print the subset of cores the feature was enabled on. Since the infrastructure now exists to display the subset of cores where a feature is enabled, lets also enable it for the Dirty Bit Management and 32-bit EL0. The 32-bit EL0 patch is only lightly tested as the AEM/TFA model firmware doesn't like mismatched AARCH32 support. Its also the least ugly version of the three or so options I considered. v1->v2: Add DBM and 32-bit EL0 code so they now display the core subset Add Ionela Voinescu review/testing tags Small comment tweak in the first patch Jeremy Linton (3): arm64: cpufeature: Display the set of cores with a feature arm64: cpufeature: Change DBM to display enabled cores arm64: cpufeature: Change 32-bit EL0 to display enabled cores arch/arm64/include/asm/cpufeature.h | 2 + arch/arm64/kernel/cpufeature.c | 70 ++++++++++++++--------------- 2 files changed, 36 insertions(+), 36 deletions(-)