From patchwork Wed Oct 25 09:57:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 13435889 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4328BC25B47 for ; Wed, 25 Oct 2023 09:57:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=ih5TR6DKuEILg+jyj/NdwNn5uVaU4hGCsrZX1KWGtw0=; b=cOsMTIl4RqwoVB NexBRKHwYQnMghD6BG5pGZ+JVJ9XPicW0FkbiAM0PSmTssEVNR8m/x2cuakG2CwTo0JotDDTUmSCB nNbqncanBJoOMJmRpfpjcf3HLytC7kCZjlvoi1wWTmmmWA3qCmaYjNNCwdbxAseCES4Gxx9Yq9xz2 DRAEFf81kreisS7poIrpc7cfL2cCPh71pdkO0bFfUi6kmEj6sbe4gw2WyTUhoM7QFNIyGzC9+Usav 7KVcC9B2NIacSOm1S55Y9HC97k2Hc3+AnvNifdA/9F3lUL00/2ODSVJM3u0tYNgWdhZWC9cnxnRoL SWIhhCDw8Iq2EJFHOVlQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qvadr-00Bt6o-0P; Wed, 25 Oct 2023 09:57:35 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qvado-00Bt5o-0o for linux-arm-kernel@lists.infradead.org; Wed, 25 Oct 2023 09:57:33 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8FE8B2F4; Wed, 25 Oct 2023 02:58:09 -0700 (PDT) Received: from e127643.arm.com (unknown [10.57.70.16]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A47483F738; Wed, 25 Oct 2023 02:57:25 -0700 (PDT) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, suzuki.poulose@arm.com, oliver.upton@linux.dev Cc: kvmarm@lists.linux.dev, James Clark , Catalin Marinas , Will Deacon , Jonathan Corbet , Russell King , Mark Rutland , Marc Zyngier , Geert Uytterhoeven , Reiji Watanabe , Zaid Al-Bassam , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 0/3] arm64: perf: Add support for event counting threshold Date: Wed, 25 Oct 2023 10:57:02 +0100 Message-Id: <20231025095710.1559601-1-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231025_025732_351551_582D3E93 X-CRM114-Status: GOOD ( 16.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Changes since v3: * Drop #include changes to KVM source files because since commit bc512d6a9b92 ("KVM: arm64: Make PMEVTYPER_EL0.NSH RES0 if EL2 isn't advertised"), KVM doesn't use ARMV8_PMU_EVTYPE_MASK anymore Changes since v2: * Split threshold_control attribute into two, threshold_compare and threshold_count so that it's easier to use * Add some notes to the first commit message and the cover letter about the behavior in KVM * Update the docs commit with regards to the split attribute Changes since v1: * Fix build on aarch32 by disabling FEAT_PMUv3_TH and splitting event type mask between the platforms * Change armv8pmu_write_evtype() to take unsigned long instead of u64 so it isn't unnecessarily wide on aarch32 * Add UL suffix to aarch64 event type mask definition ---- FEAT_PMUv3_TH (Armv8.8) is a new feature that allows conditional counting of PMU events depending on how much the event increments on a single cycle. Two new config fields for perf_event_open have been added, and a PMU cap file for reading the max_threshold. See the second commit message and the docs in the last commit for more details. The feature is not currently supported on KVM guests, and PMMIR is set to read as zero, so it's not advertised as available. But it can be added at a later time. Writes to PMEVTYPER.TC and TH from guests are already RES0. The change has been validated on the Arm FVP model: # Zero values, works as expected (as before). $ perf stat -e dtlb_walk/threshold=0,threshold_compare=0/ -- true 5962 dtlb_walk/threshold=0,threshold_compare=0/ # Threshold >= 255 causes count to be 0 because dtlb_walk doesn't # increase by more than 1 per cycle. $ perf stat -e dtlb_walk/threshold=255,threshold_compare=2/ -- true 0 dtlb_walk/threshold=255,threshold_compare=2/ # Keeping comparison as >= but lowering the threshold to 1 makes the # count return. $ perf stat -e dtlb_walk/threshold=1,threshold_compare=2/ -- true 6329 dtlb_walk/threshold=1,threshold_compare=2/ Applies to kvmarm/next (54552d5bf954) James Clark (3): arm: perf: Include threshold control fields valid in PMEVTYPER mask arm64: perf: Add support for event counting threshold Documentation: arm64: Document the PMU event counting threshold feature Documentation/arch/arm64/perf.rst | 56 +++++++++++++++++++++ arch/arm/include/asm/arm_pmuv3.h | 3 ++ arch/arm64/include/asm/arm_pmuv3.h | 4 ++ drivers/perf/arm_pmuv3.c | 79 +++++++++++++++++++++++++++++- include/linux/perf/arm_pmuv3.h | 4 +- 5 files changed, 144 insertions(+), 2 deletions(-) base-commit: 54552d5bf9543bbc1edfd32c4e4b8a56ec4f9711