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Sun, 31 Dec 2023 09:39:00 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id t27-20020ac243bb000000b0050e798243a7sm2233233lfl.177.2023.12.31.09.38.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Dec 2023 09:38:59 -0800 (PST) From: Dmitry Baryshkov Subject: [PATCH 0/2] ARM: implement cacheinfo support (for v7/v7m) Date: Sun, 31 Dec 2023 19:38:56 +0200 Message-Id: <20231231-armv7-cacheinfo-v1-0-9e8d440b59d9@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIADCnkWUC/x2MQQqAIBAAvyJ7TkglpL4SHRZbcw9pKEgg/j0J5 jKHmQaFMlOBTTTIVLlwikPUJMAFjBdJPoeDnrVRA4n5rlY6dIE4+iRXj4sxSMYqglE9mTy//3E /ev8Azbr0AmEAAAA= To: Russell King Cc: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1231; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=ZbnkF096dvQGlLCSukEfSJ0VKpmFN+Kk69iSZdj9Crk=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlkaczSNiTf9HQFVkXjC/zbvwQY5RW4pEXfvDET Zjntl+IzneJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZZGnMwAKCRCLPIo+Aiko 1Xu6B/41D9u8tN4na0LDhbVVyfTej377cgDODkEVyEHduVEo/AEyVyQPYN8uWDYPo2l93g3aYPP hFo7+yLhDY4PgLP0R9vkWTYlPvi5oA1g5z9jRs4ILBscMUlOIg59ppcsoHQtkMjU9ZCEHUcRv0S zx7t9gH5HEGaqJn8fTikSAkicb0NXSnOgLiW6xJ+/5t6IxOEXcbAxGg0vn2GtFj2O2yfcOZyV6R 2YhdrrVfzFgYNI6a6zxDw3RBt9R+qh5N9R1EExXyzYbLppFRrJ4UUCmwQdfpYTyZbrP+Sibrmo7 eZ5+C+R/X18lWk4Pdm61biT96U8ly72apPuV+JqxIr5pMUSi X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231231_093903_910981_BC47EA59 X-CRM114-Status: UNSURE ( 9.66 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Follow the ARM64 platform and implement simple cache information driver. As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is limited to the ARMv7 / ARMv7M, providing simple fallback or just returning -EOPNOTSUPP in case of older platforms. In theory we should be able to skip CLIDR reading and assume that Dcache and Icache (or unified L1 cache) always exist if CTR is supported and returns sensible value. However I think this better be handled by the maintainers of corresponding platforms. Signed-off-by: Dmitry Baryshkov --- Dmitry Baryshkov (2): ARM: add CLIDR accessor functions ARM: implement cacheinfo support arch/arm/Kconfig | 1 + arch/arm/include/asm/cache.h | 6 ++ arch/arm/include/asm/cachetype.h | 13 ++++ arch/arm/kernel/Makefile | 1 + arch/arm/kernel/cacheinfo.c | 164 +++++++++++++++++++++++++++++++++++++++ include/linux/cacheinfo.h | 2 +- 6 files changed, 186 insertions(+), 1 deletion(-) --- base-commit: 39676dfe52331dba909c617f213fdb21015c8d10 change-id: 20231231-armv7-cacheinfo-9fa533ae371e Best regards,