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Tue, 06 Feb 2024 06:37:57 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCUu96QIev3G7AKOTetfby9vEMbsek5UkU7upCeDF5tSF7c/MeK2fVG0fw4hzpDAaWaMvaXJRMsNBEsNDUI+69YY2K/lDyZjhxOhCHbUokqg+6sDTig3NcwmjlTm6pYpFhpvfCMbdEYh4nxSMlnlSN5aIOWh0Bp843YDMliA2q8NqVIInjiw5e5mY2j8rNnhLyVt0UN56mOHRY8LnVeIDo2ZuBnKOfag9DpCkHWLeTTQC/EmDij29Wi49dSclEb/rXgr8rERdEg4HKCEaFe8AbhsF9btBV6y1TPC9s1DnPhzLVAICklNMlAZDYWOqXKawqEPCO6mgMCjoss38HGP4XfV2XudnTswqnvDHWmGiuNUIboBfIOJw2+pDSqxCSQEvisMERpTkYEjtZLNL2ucvdlOwBFZWmMOxgSbKvVLWyzY6rM2QYap Received: from blmsp.fritz.box ([2001:4091:a246:821e:6f3b:6b50:4762:8343]) by smtp.gmail.com with ESMTPSA id e22-20020a1709062c1600b00a37585d5dcesm1224418ejh.51.2024.02.06.06.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Feb 2024 06:37:57 -0800 (PST) From: Markus Schneider-Pargmann To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Santosh Shilimkar Cc: Andrew Davis , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Markus Schneider-Pargmann Subject: [PATCH 0/4] soc: ti: k3-socinfo: Add support for nvmem cells Date: Tue, 6 Feb 2024 15:37:07 +0100 Message-ID: <20240206143711.2410135-1-msp@baylibre.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240206_063800_330813_09EF75A5 X-CRM114-Status: GOOD ( 10.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, am62 has a number of efuse fields that are situated in the device range of the current chipid device node. As other devices require these information as well, I am trying to establish a new nvmem layout for the information available in this register range. In this series the conflicting chipid driver is updated to support nvmem-cells and the chipid node gets the register range removed and replaced with nvmem cells on am62. In a follow-up series the opp table will be updated. Best, Markus Markus Schneider-Pargmann (4): nvmem: core: Read into buffers larger than data dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells soc: ti: k3-socinfo: Add support for nvmem cells arm64: dts: ti: k3-am62-wakeup: Add chip efuse nodes .../bindings/hwinfo/ti,k3-socinfo.yaml | 23 ++++++- arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 36 +++++++++- drivers/nvmem/core.c | 6 +- drivers/soc/ti/k3-socinfo.c | 67 +++++++++++++------ 4 files changed, 107 insertions(+), 25 deletions(-)